Logic semiconductor devices

• US 10,170,421 B2
• Filed: 07/12/2017
• Issued: 01/01/2019
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Azmat, Raheel, Rwik, Sengupta, Kim, Su-Hyeon, Park, Chul-Hong, Lim, Jae-Hyoung
• Primary Examiner(s): Yushin, Nikolay
• Application Number:
  US15/647,467
• Publication Number:
  US 20170309569A1
• Time in Patent Office: 538 Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Claims

1. A logic semiconductor device, comprising:

a plurality of active patterns extending in a first direction and being spaced apart from each other in a second direction, the first and second directions being perpendicular to each other;

an isolation layer defining the active patterns;

a plurality of gate patterns extending in the second direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the first direction and at least one of the gate patterns being on the plurality of active patterns;

active contacts connected to upper portions of the active patterns adjacent to the gate patterns;

a plurality of sub-wirings integrally connected to the active contacts, the sub-wirings extending in the first direction; and

wirings extending in the second direction over the sub-wirings.

2. The logic semiconductor device of claim 1, further comprising gate contacts disposed on the gate patterns.

3. The logic semiconductor device of claim 2, wherein top surfaces of the sub-wirings and the gate contacts are coplanar with each other relative to the active patterns.

4. The logic semiconductor device of claim 2, wherein the wirings are disposed at a single level, and each of the wirings overlaps each of the gate patterns.

5. The logic semiconductor device of claim 4, further comprising first contacts connecting the gate contacts and the wirings.

6. The logic semiconductor device of claim 1, further comprising silicide patterns formed at the upper portions of the active patterns adjacent to the gate patterns,

wherein the active contacts are in contact with the silicide patterns.

7. A logic semiconductor device, comprising:

a plurality of active patterns extending in a first direction and being spaced apart from each other in a second direction, the first and second direction being perpendicular to each other;

an isolation layer defining the active patterns;

a plurality of gate patterns extending in the second direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the first direction and at least one of the gate patterns being on the plurality of active patterns;

a plurality of lower wirings extending in the first direction over the gate patterns and being spaced apart from each other in the second direction, the lower wirings having a straight line shape; and

a plurality of upper wirings extending in the second direction over the lower wirings and being spaced apart from each other in the first direction, the upper wirings having a straight line shape.

8. The logic semiconductor device of claim 7, wherein the lower wirings and the upper wirings do not include a protrusion or a diverging portion.

9. The logic semiconductor device of claim 7, further comprising:

first contacts connecting the gate patterns or active patterns to the lower wirings; and

second contacts connecting the upper wirings and the lower wirings.

10. The logic semiconductor device of claim 7, wherein the upper wirings serve as input/output pins, and the lower wirings serve as a gate pick-up wiring and a power rail.

11. A logic semiconductor device, comprising:

an active pattern;

a gate pattern on the active pattern and extending in a first direction to cross over the active pattern;

an upper wiring aligned with the gate pattern and extending in the first direction; and

a lower wiring between the gate pattern and the upper wiring and being aligned with the active pattern so as to extend in a second direction, the upper wiring crossing over the lower wiring.

12. The logic semiconductor device of claim 11, further comprising:

an interlayer insulating layer between the upper wiring and the lower wiring; and

a contact extending through the interlayer insulating layer so as to connect the lower wiring to the upper wiring.

13. The logic semiconductor device of claim 11, wherein the lower wiring is one of a plurality of lower wirings;

and

wherein the plurality of lower wirings comprises a power rail, the power rail having a width in the first direction that is greater than widths of other ones of the plurality of lower wirings.

14. The logic semiconductor device of claim 11, further comprising:

an insulation block that is configured to divide the lower wiring into a first lower wiring portion and a second lower wiring portion.

15. The logic semiconductor device of claim 14, wherein the active pattern is a first active pattern and the gate pattern is a first gate pattern, further comprising:

a second active pattern;

a second gate pattern on the second active pattern;

a first gate contact on the first gate pattern;

a second gate contact on the second gate pattern;

a first contact that connects the first lower wiring portion to the first gate contact; and

a second contact that connects the second lower wiring portion to the second gate contact.

16. The logic semiconductor device of claim 11, further comprising:

a gate contact on the gate pattern;

a plurality of interlayer insulating layers between the upper wiring and the gate contact; and

a through contact extending through the plurality of interlayer insulating layers so as to connect the upper wiring to the gate contact.

17. The logic semiconductor device of claim 11, wherein the lower wiring is one of a plurality of lower wirings, further comprising:

a plurality of insulation blocks, each of the plurality of lower wirings being divided by at least one of the plurality of insulation blocks into multiple portions.

18. The logic semiconductor device of claim 17, wherein the plurality of insulation blocks is arranged in a staggered configuration along the second direction when the logic semiconductor device is viewed from a plan view.