Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors

• US 10,170,479 B2
• Filed: 05/26/2017
• Issued: 01/01/2019
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Liu, Zuoguang, Mehta, Sanjay C., Yamashita, Tenko
• Primary Examiner(s): Whalen, Daniel
• Application Number:
  US15/606,736
• Publication Number:
  US 20180006037A1
• Time in Patent Office: 585 Days
• Field of Search: None
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a fin field effect transistor (finFET) with a doped substrate region, including forming a plurality of vertical fins on a substrate, forming a first dopant source on one or more of the plurality of vertical fins, wherein the first dopant source is not formed on at least one vertical fin, forming a second dopant source on the at least one vertical fin that does not have a first dopant source formed thereon, and heat treating the plurality of vertical fins on the substrate, the first dopant source, and the second dopant source, wherein the heat treatment is sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate.

Claims

1. A complementary metal oxide semiconductor (CMOS) device with punch-through stops/wells, comprising:

one or more vertical fin(s) on a substrate in a first region and one or more vertical fin(s) on the substrate in a second region, wherein the first region is adjacent to the second region;

a first dopant source on the one or more vertical fin(s) in the first region, wherein the first dopant source extends along a portion of the length of each of the one or more vertical fins in the first region;

a second dopant source on the one or more vertical fin(s) in the second region, wherein the second dopant source extends along a portion of the length of each of the one or more vertical fins in the second region;

a first doped region in the substrate forming a first punch-through stop/well below the first dopant source, wherein the first punch-through stop/well includes a first dopant at a concentration in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

a second doped region in the substrate forming a second punch-through stop/well below the second dopant source, wherein the second punch-through stop/well includes a second dopant at a concentration in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

an isolation spacer on the first dopant source and the second dopant source, wherein the thickness of the first dopant source and second dopant source are in the range of about 50 nm to about 150 nm; and

a gate dielectric layer on at least a portion of the isolation spacer, at least a portion of the one or more vertical fins) in the first region, and at least a portion of the one or more vertical fin(s) in the second region.

2. The CMOS device of claim 1, wherein the first punch-through stop/well is doped with boron, and the second punch-through stop/well is doped with phosphorous.

3. The CMOS device of claim 1, further comprising a gate electrode layer on the one or more vertical fin(s) in the first region, and a gate electrode layer on the one or more vertical fin(s) in the second region.

4. The CMOS device of claim 1, wherein the first dopant source and the second dopant source are insulating glasses that form an isolation region between the one or more fin(s) in the second region and the one or more vertical fin(s) in the first region.

5. The CMOS device of claim 1, where the isolation spacer has a thickness in the range of about 5 nm to about 10 nm.

6. The CMOS device of claim 1, wherein the first punch-through stop/well extends a distance into the substrate in the range of about 10 nm to about 30 nm, and the second punch-through stop/well extends into the substrate a distance in the range of about 10 nm to about 30 nm.

7. The CMOS device of claim 1, wherein the first dopant and the second dopant are not aluminum, gallium, indium, or antimony.

8. The CMOS device of claim 1, wherein one of the first dopant or the second dopant is an n-type dopant, and the other of the first dopant or the second dopant is a p-type dopant.

9. The CMOS device of claim 1, wherein the first dopant is boron and the second dopant is phosphorous.

10. The CMOS device of claim 1, wherein the first doped region in the substrate at least partially overlaps the second doped region in the substrate to form a compensated interface.

11. The CMOS device of claim 10, wherein the material of the second dopant source is phospho-silicate glass (PSG) or boro-silicate glass (BSG), and wherein the material of the second dopant source is different from the material of the first dopant source.

12. The CMOS device of claim 1, wherein the one or more vertical fin(s) in the first region are doped to form an n-type field effect transistor and the one or more vertical fin(s) in the second region are doped to form a p-type field effect transistor.

13. A complementary metal oxide semiconductor (CMOS) device with punch-through stops/wells, comprising:

one or more vertical fin(s) on a substrate in a first region and one or more vertical fin(s) on the substrate in a second region, where the first region is adjacent to the second region, and the one or more vertical fin(s) in the first region are doped to form an n-type field effect transistor and the one or more vertical fin(s) in the second region are doped to form a p-type field effect transistor;

a first dopant source on the one or more vertical fin(s) in the first region, wherein the first dopant source extends along a portion of the length of each of the one or more vertical fins in the first region;

a second dopant source on the one or more vertical fin(s) in the second region, wherein the second dopant source extends along a portion of the length of each of the one or more vertical fins in the second region;

a first doped region in the substrate forming a first punch-through stop/well below the first dopant source, wherein the first punch-through stop/well includes a first dopant at a concentration in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

a second doped region in the substrate forming a second punch-through stop/well below the second dopant source;

an isolation spacer on the first dopant source and the second dopant source, wherein the thickness of the first dopant source and second dopant source are in the range of about 50 nm to about 150 nm; and

a gate dielectric layer on at least a portion of the isolation spacer, at least a portion of the one or more vertical fin(s) in the first region, and at least a portion of the one or more vertical fin(s) in the second region.

14. The CMOS device of claim 13, wherein the material of the second dopant source is phospho-silicate glass (PSG) or boro-silicate glass (BSG), and wherein the material of the second dopant source is different from the material of the first dopant source.

15. The CMOS device of claim 13, wherein the vertical fins have a width in the range of about 6 nm to about 20 nm.

16. A complementary metal oxide semiconductor (CMOS) device with punch-through stops/wells, comprising:

one or more vertical fin(s) on a substrate in a first region and one or more vertical fin(s) on the substrate in a second region, where the first region is adjacent to the second region, and the one or more vertical fin(s) in the first region are doped to form an n-type field effect transistor and the one or more vertical fin(s) in the second region are doped to form a p-type field effect transistor;

a first dopant source on the one or more vertical fin(s) in the first region, wherein the first dopant source is borosilicate glass (BSG), where the boron is at a concentration in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

a second dopant source on the one or more vertical fin(s) in the second region, wherein the second dopant source is phosphosilicate glass (PSG), where the phosphorous is at a concentration in the range of about 1×

10′

⁷/cm³ to about 1×

10¹⁹/cm³;

a first doped region in the substrate forming a first punch-through stop/well below the first dopant source;

a second doped region in the substrate forming a second punch-through stop/well below the second dopant source, wherein the second punch-through stop/well includes a second dopant at a concentration in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

an isolation spacer on the first dopant source and the second dopant source, wherein the thickness of the first dopant source and second dopant source are in the range of about 50 nm to about 150 nm; and

a gate dielectric layer on at least a portion of the isolation spacer, at least a portion of the one or more vertical fin(s) in the first region, and at least a portion of the one or more vertical fin(s) in the second region.