Semiconductor storage device comprising peripheral circuit, shielding layer, and memory cell array

• US 10,170,486 B2
• Filed: 03/29/2016
• Issued: 01/01/2019
• Est. Priority Date: 09/21/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Atsumi, Tomoaki, Okuda, Takashi
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US15/083,364
• Publication Number:
  US 20160211267A1
• Time in Patent Office: 1,008 Days
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

Claims

1. A semiconductor storage device comprising:

a first transistor;

a conductive film over the first transistor; and

a plurality of second transistors each comprising a channel region,

wherein a channel region of the first transistor comprises silicon,

wherein each of the plurality of channel regions of second transistors comprises an oxide semiconductor, and

wherein entirety of the plurality of second transistors overlaps with the conductive film.

2. The semiconductor storage device according to claim 1, wherein the first transistor is formed by utilizing a semiconductor substrate.

3. The semiconductor storage device according to claim 1, further comprising a second conductive film over the plurality of second transistors and a plurality of third transistors over the second conductive film.

4. The semiconductor storage device according to claim 1, wherein the conductive film is configured to be supplied with a ground potential.

5. The semiconductor storage device according to claim 1, wherein the first transistor is electrically connected to at least one of the plurality of second transistors through a contact plug comprising a same layer as the conductive film.

6. A semiconductor storage device comprising:

a first transistor;

a first conductive film over the first transistor;

a plurality of second transistors over the first conductive film;

a second conductive film over the plurality of second transistors; and

a plurality of third transistors over the second conductive film,

wherein entirety of the plurality of second transistors overlaps with the first conductive film, and

wherein entirety of the plurality of third transistors overlaps with the second conductive film.

7. The semiconductor storage device according to claim 6, wherein the first transistor is formed by utilizing a semiconductor substrate.

8. The semiconductor storage device according to claim 6, wherein the first conductive film is configured to be supplied with a ground potential.

9. The semiconductor storage device according to claim 6, wherein the first transistor is electrically connected to at least one of the plurality of second transistors through a contact plug comprising a same layer as the first conductive film.