Device having an inter-layer via (ILV), and method of making same

• US 10,170,487 B2
• Filed: 10/25/2016
• Issued: 01/01/2019
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Tsung-Hsien, Cheng, Hong-Chen, Lee, Cheng Hung, Liao, Hung-Jen
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US15/333,439
• Publication Number:
  US 20170047333A1
• Time in Patent Office: 798 Days
• Field of Search: 257401
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.

Claims

1. A three-dimensional integrated circuit comprising:

a first transistor on a first level;

a word line coupled to the first transistor;

a first via coupled to the first transistor;

a second transistor on a second level different from the first level;

another word line coupled to the second transistor; and

a second via coupled between the first transistor and the second transistor.

2. The three-dimensional integrated circuit of claim 1, further comprising:

an insulating layer between the first level and the second level, the first transistor being part of a first memory device, and the second transistor being part of a second memory device.

3. The three-dimensional integrated circuit of claim 1, further comprising:

a third via coupled to the word line and the first transistor, the third via being different from the second via.

4. The three-dimensional integrated circuit of claim 3,

wherein the another word line is coupled to the third via, and the first via being further coupled to a ground terminal.

5. The three-dimensional integrated circuit of claim 1, further comprising:

a third via, and

a bit line coupled to the second transistor by at least the third via.

6. The three-dimensional integrated circuit of claim 1, further comprising:

a third via coupled to the second transistor and the first via, the second transistor comprising;

a first region coupled to a ground terminal, and

a second region coupled to the third via.

7. The three-dimensional integrated circuit of claim 6, further comprising:

a fourth via coupled to a first region of the first transistor; and

a fifth via coupled between the first region of the second transistor and the ground terminal.

8. The three-dimensional integrated circuit of claim 1, wherein the second via is an inter-layer via having a height ranging from about 30 nanometers (nm) to about 70 nm.

9. The three-dimensional integrated circuit of claim 1, wherein at least one of the first via, the second via or a third via has a circular shape or a rectangular shape.

10. A three-dimensional integrated circuit, comprising:

a first transistor;

a first word line coupled to the first transistor;

a first via coupled to at least a first region of the first transistor;

a second transistor under the first transistor;

a second word line coupled to the second transistor, and

a second via coupled to a second region of the first transistor, the second region of the first transistor being different from the first region of the first transistor.

11. The three-dimensional integrated circuit of claim 10, further comprising:

a third via coupled between the first word line and the second word line.

12. The three-dimensional integrated circuit of claim 10, wherein the second region of the first transistor is coupled to a ground terminal.

13. The three-dimensional integrated circuit of claim 10, wherein the second transistor comprises a first region configured to be electrically floating.

14. The three-dimensional integrated circuit of claim 10, further comprising:

a third via between the first transistor and the second transistor.

15. The three-dimensional integrated circuit of claim 14, further comprising:

a fourth via coupled between a region of the second transistor and a ground terminal.

16. The three-dimensional integrated circuit of claim 15, further comprising:

a fifth via coupled to another region of the second transistor, wherein the third via is coupled to the first via and the fifth via.

17. The three-dimensional integrated circuit of claim 14, wherein the third via has a diameter ranging from about 10.5 nanometers (nm) to about 11.5 nm.

18. The three-dimensional integrated circuit of claim 14, wherein the third via is an inter-layer via having a height ranging from about 75 nanometers (nm) to about 140 nm.

19. A three-dimensional semiconductor device, comprising:

a first memory device;

a first via coupled to a first portion of the first memory device;

a first word line coupled to the first memory device;

a second memory device above the first memory device;

a second word line coupled to the second memory device;

an insulating layer between the first memory device and the second memory device; and

a second via coupled to the first memory device and the second memory device.

20. The three-dimensional semiconductor device of claim 19, further comprising:

the second word line being above the first word line and the first memory device;

a third via coupled to a first portion of the second memory device;

a fourth via coupled between the first word line and the second word line; and

a fifth via coupled to a second portion of the second memory device different from the first portion of the second memory device.