Device having an inter-layer via (ILV), and method of making same
First Claim
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1. A three-dimensional integrated circuit comprising:
- a first transistor on a first level;
a word line coupled to the first transistor;
a first via coupled to the first transistor;
a second transistor on a second level different from the first level;
another word line coupled to the second transistor; and
a second via coupled between the first transistor and the second transistor.
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Abstract
A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.
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Citations
20 Claims
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1. A three-dimensional integrated circuit comprising:
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a first transistor on a first level; a word line coupled to the first transistor; a first via coupled to the first transistor; a second transistor on a second level different from the first level; another word line coupled to the second transistor; and a second via coupled between the first transistor and the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A three-dimensional integrated circuit, comprising:
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a first transistor; a first word line coupled to the first transistor; a first via coupled to at least a first region of the first transistor; a second transistor under the first transistor; a second word line coupled to the second transistor, and a second via coupled to a second region of the first transistor, the second region of the first transistor being different from the first region of the first transistor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A three-dimensional semiconductor device, comprising:
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a first memory device; a first via coupled to a first portion of the first memory device; a first word line coupled to the first memory device; a second memory device above the first memory device; a second word line coupled to the second memory device; an insulating layer between the first memory device and the second memory device; and a second via coupled to the first memory device and the second memory device. - View Dependent Claims (20)
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Specification