×

Device having an inter-layer via (ILV), and method of making same

  • US 10,170,487 B2
  • Filed: 10/25/2016
  • Issued: 01/01/2019
  • Est. Priority Date: 09/27/2013
  • Status: Active Grant
First Claim
Patent Images

1. A three-dimensional integrated circuit comprising:

  • a first transistor on a first level;

    a word line coupled to the first transistor;

    a first via coupled to the first transistor;

    a second transistor on a second level different from the first level;

    another word line coupled to the second transistor; and

    a second via coupled between the first transistor and the second transistor.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×