Uniform bottom spacer for vertical field effect transistor

• US 10,170,582 B1
• Filed: 09/13/2017
• Issued: 01/01/2019
• Est. Priority Date: 09/13/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Belyansky, Michael P., Chi, Cheng, De Silva, Ekmini Anuja, Yamashita, Tenko
• Primary Examiner(s): Dinke, Bitew A
• Application Number:
  US15/703,105
• Time in Patent Office: 475 Days
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of forming a semiconductor structure includes forming a protective liner comprising a metal oxide above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a NON hardmask positioned on top of the fin, removing the protective liner from top surfaces of the semiconductor substrate and NON hardmask, the protective liner remaining on sidewalls of the fin and the NON hardmask, depositing a first dielectric layer, simultaneously removing top portions of the first dielectric layer and NON hardmask, the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate, removing the protective liner, the removing of the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin that is subsequently filled with a second dielectric layer.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a protective liner above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a nitride-oxide-nitride hardmask positioned on top of the fin, wherein the protective liner comprises a metal oxide material;

removing the protective liner from a top surface of the semiconductor substrate and a top surface of the nitride-oxide-nitride hardmask, wherein the protective liner remains on sidewalls of the fin and the nitride-oxide-nitride hardmask;

forming a first dielectric layer above and in direct contact with the semiconductor substrate, the protective liner and the top surface of the nitride-oxide-nitride hardmask;

simultaneously removing top portions of the first dielectric layer and the nitride-oxide-nitride hardmask, wherein the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate;

removing the protective liner from the semiconductor structure, wherein removing the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin; and

forming a second dielectric layer, the second dielectric layer fills the opening between the first dielectric layer and the bottom portion of the fin.

2. The method of claim 1, wherein forming the second dielectric layer comprises:

etching the second dielectric layer until a top surface of the second dielectric layer is coplanar with a top surface of the first dielectric layer such that a thickness of the first dielectric layer and a thickness of the second dielectric layer are substantially the same.

3. The method of claim 1, wherein the nitride-oxide-nitride hardmask comprises a first layer directly above the fin, a second layer interpose between the first layer and a third layer, the third layer directly above the second layer, wherein the first layer and the third layer comprise silicon nitride (SiN) and the second layer comprises silicon dioxide (SiO2).

4. The method of claim 1, wherein the metal oxide material is capable of being deposited using atomic layer deposition (ALD) and removed by a Standard Cleaning 1 (SC1) solution.

5. The method of claim 1, wherein the protective liner has a thickness varying from approximately 1 nm to approximately 5 nm.

6. The method of claim 1, wherein the metal oxide material comprises titanium dioxide (TiO₂), titanium nitride (TiN), titanium oxycarbide (TiCO), titanium oxynitride (TiON), titanium oxycarbon nitride (TiOCN), hafnium oxide (HfO₂), tungsten oxide (WO₃), tantalum oxide (Ta₂O₅), or zirconium dioxide (ZrO₂).

7. The method of claim 1, wherein forming the first dielectric layer comprises using a directional deposition method such that a thickness of the first dielectric layer above the semiconductor substrate and in contact with the bottom portion of the fin is larger than a thickness of a top portion of the first dielectric layer.

8. The method of claim 7, wherein the directional deposition method comprises a High-Density Plasma CVD.

9. The method of claim 1, wherein the second dielectric layer comprises silicon oxycarbide, silicon oxide, silicon nitride, silicon oxynitride, a low-k material, or any combination thereof.

10. A method of forming a semiconductor structure, the method comprising:

forming a fin extending upward from a semiconductor substrate;

forming a nitride-oxide-nitride hardmask above and in direct contact with the fin, the nitride-oxide-nitride hardmask comprising a first layer in direct contact with the fin, a second layer above and in direct contact with the first layer, and a third layer above and in direct contact with the second layer;

conformally depositing a protective liner above and in direct contact with the semiconductor substrate and the fin, the protective liner comprising a metal oxide material;

removing the protective liner from a top surface of the semiconductor substrate and a top surface of the third layer of the nitride-oxide-nitride hardmask, wherein the protective liner remains on sidewalls of the fin and the nitride-oxide-nitride hardmask;

depositing a first dielectric layer above and in direct contact with the semiconductor substrate, the protective liner and the top surface of the third layer;

simultaneously removing top portions of the first dielectric layer and the third layer of the nitride-oxide-nitride hardmask, the first dielectric layer and the third layer comprise substantially similar materials, wherein the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate;

removing the protective liner from the semiconductor structure, wherein removing the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin;

conformally depositing a second dielectric layer, the second dielectric layer fills the opening between the first dielectric layer and the bottom portion of the fin; and

etching the second dielectric layer until a top surface of the second dielectric layer is coplanar with a top surface of the first dielectric layer such that a thickness of the first dielectric layer and a thickness of the second dielectric layer are substantially the same, wherein the first dielectric layer and the second dielectric layer comprise a bottom spacer.

11. The method of claim 10, wherein the first layer and the third layer of the nitride-oxide-nitride hardmask comprise silicon nitride (SiN) and the second layer comprises silicon dioxide (SiO2).

12. The method of claim 10, wherein the metal oxide material is capable of being deposited using atomic layer deposition (ALD) and removed (strippable) by a Standard Cleaning 1 (SC1) solution.

13. The method of claim 10, wherein the metal oxide material comprises titanium dioxide (TiO₂), titanium nitride (TiN), titanium oxycarbide (TiCO), titanium oxynitride (TiON), titanium oxycarbon nitride (TiOCN), hafnium oxide (HfO₂), tungsten oxide (WO₃), tantalum oxide (Ta₂O₅), or zirconium dioxide (ZrO₂).

14. The method of claim 10, wherein the protective liner has a thickness varying from approximately 1 nm to approximately 5 nm.

15. The method of claim 10, wherein depositing the first dielectric layer comprises using a directional deposition method such that a thickness of the first dielectric layer above the semiconductor substrate and in contact with the bottom portion of the fin is larger than a thickness of a top portion of the first dielectric layer.

16. The method of claim 15, wherein the directional deposition method comprises a High-Density Plasma CVD.

17. The method of claim 10, wherein the second dielectric layer comprises silicon oxycarbide, silicon oxide, silicon nitride, silicon oxynitride, a low-k material, or any combination thereof.