Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor

• US 10,170,621 B2
• Filed: 05/23/2017
• Issued: 01/01/2019
• Est. Priority Date: 05/24/2016
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Original Assignee: Commissariat a L'Energie Atomique (French Alternative Energies and Atomic Energy Commission)
• Inventors: Reboh, Shay, Batude, Perrine, Piegas Luce, Flavia
• Primary Examiner(s): Woldegeorgis, Ermias
• Application Number:
  US15/602,829
• Publication Number:
  US 20170345931A1
• Time in Patent Office: 588 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors

Abstract

Method of making a transistor, comprising the following steps:

• • make a gate and a first spacer on a first channel region of a first crystalline semiconducting layer;
  • make first crystalline semiconductor portions on the second source and drain regions;
  • make the second regions amorphous and dope them;
  • recrystallise the second regions and activate the dopants present in the second regions;
  • remove the first portions;
  • make a second spacer thicker than the first spacer;
  • make second doped crystalline semiconductor portions on the second regions, said second portions and the second regions of the first layer together form the source and drain of the transistor.

Claims

1. Method of making a transistor, comprising:

forming a gate and a first dielectric spacer in contact with the side walls of the gate, on a first region of a first layer that will form the transistor channel, the first layer being a crystalline semiconducting layer;

forming first portions of crystalline semiconductor on second regions of the first layer that will form part of the transistor source and drain;

making at least the second regions of the first layer amorphous and doping them;

recrystallizing at least the semiconductor in the second regions of the first layer and activating the dopants present at least in the semiconductor of the second regions of the first layer;

removing the first portions;

forming a second dielectric spacer in contact with the lateral walls of the gate such that the thickness of the second dielectric spacer is more than the thickness of the first dielectric spacer;

forming second portions of doped crystalline semiconductor on the second regions of the first layer such that at least said second portions and the second regions of the first layer together form the source and drain of the transistor.

2. Method according to claim 1, in which the first layer is a surface layer of a semiconductor on insulator type substrate.

3. Method according to claim 2, in which the transistor is of the FDSOI type and the thickness of the first layer is between about 4 nm and 8 nm.

4. Method according to claim 1, further comprising forming, between the forming the gate and the first dielectric spacer and the forming the first portions, an etching stop layer on the second regions of the first layer, and removing the first portions includes etching of the first portions until reaching the etching stop layer.

5. Method according to claim 4, further comprising removing, between the removal of the first portions and the forming the second portions, the etching stop layer.

6. Method according to claim 1, in which the thickness of the first dielectric spacer is between about 1 nm and 3 nm.

7. Method according to claim 1, in which the forming of the second dielectric spacer includes depositing dielectric material around the first dielectric spacer such that said dielectric material and the first dielectric spacer together form the second dielectric spacer, or the forming of the second dielectric spacer includes removal of the first dielectric spacer followed by deposition of dielectric material forming the second dielectric spacer.

8. Method according to claim 1, further comprising etching, between the forming the second dielectric spacer and the forming the second portions, an upper part of the second regions of the first layer such that the second portions are made on remaining parts of the second regions of the first layer and partially facing the first region of the first layer.

9. Method according to claim 1, in which the first and second portions are made by epitaxy.

10. Method according to claim 1, in which the amorphisation and doping of the second regions of the first layer include implementation of a single ion implantation of doping species in the second regions of the first layer.

11. Method according to claim 1, in which the amorphisation and doping of the second regions of the first layer include a first ion implantation of non-doping species in the second regions of the first layer and a second ion implantation of doping species in the second regions of the first layer.

12. Method according to claim 1, in which the recrystallisation and activation of dopants include the use of at least one of:

annealing under an inert atmosphere at a temperature between about 500°

C. and 800°

C.,

local heating of the semiconductor containing the dopants by laser.

13. Method according to claim 1, in which:

amorphisation and doping are implemented such that they also result in amorphisation and doping of a lower part of the first portions and such that the semiconductor of an upper part of the first portions is kept in a crystalline state, and

recrystallisation and activation of the dopants are done such that the semiconductor of the lower part of the first portions is also recrystallised and that dopants present in the semiconductor of the lower part of the first portions are also activated.

14. Method according to claim 1, in which the first layer comprises silicon or SiGe comprising a proportion of germanium between about 20% and 60%.

15. Method according to claim 1, in which:

when the transistor is of the NMOS type, the first and/or second portions comprise N type doped silicon and/or or silicon strained in tension, and

when the transistor is of the PMOS type, the first portions comprise P type doped silicon and/or silicon strained in compression, and/or the second portions comprise P type doped SiGe for which the proportion of germanium is between 20% and 60%.