GaN circuit drivers for GaN circuit loads

• US 10,170,922 B1
• Filed: 02/23/2018
• Issued: 01/01/2019
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Cheng, Diana J
• Application Number:
  US15/903,398
• Time in Patent Office: 312 Days
• Field of Search: 327108-112, 257 76, 257194, 257E29089, 257E27016, 257E29246
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Claims

1. An electronic circuit comprising:

a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is connected to a ground and the low side switch drain is connected to a switch node;

a low side switch driver circuit having an output connected to the low side switch control gate;

a GaN-based high side switch having a high side switch control gate, a high side switch source and a high side switch drain, wherein the high side switch source is connected to the switch node and the high side switch drain is connected to a voltage source; and

a high side switch driver circuit having an output connected to the high side switch control gate;

wherein the low side switch driver circuit is disposed on a unitary silicon-based die that includes a control circuit configured to control the low side switch driver circuit and the high side switch driver circuit; and

a GaN-based level shift circuit configured receive a drive signal from the control circuit, level shift the drive signal and transmit a level shifted drive signal to the high side switch driver circuit.

2. The electronic circuit of claim 1 wherein the high side switch driver circuit includes a level shift receiver coupled to the level shift circuit and the level shift receiver includes a signal modulator.

3. The electronic circuit of claim 1 wherein the level shift circuit includes an inverter having a resistor pull up and a pull down transistor.

4. The electronic circuit of claim 1 wherein the GaN-based low side switch is disposed on a first GaN-based die, the GaN-based high side switch is disposed on a second GaN-based die, the low side switch driver circuit is disposed on a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

5. The electronic circuit of claim 4 wherein a GaN-based level shift circuit is disposed on a third GaN-based die.

6. The electronic circuit of claim 1 further comprising one or more pulse generators.

7. The electronic circuit of claim 1 further comprising a shoot through protection circuit configured to prevent simultaneous conduction of the high side and low side switches.

8. The electronic circuit of claim 1 wherein the high side switch driver circuit is disposed on a silicon-based die and includes a receiver circuit configured to receive the transmitted level shifted drive signal.

9. The electronic circuit of claim 1 wherein the unitary silicon-based die is a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

10. A power conversion circuit comprising:

a GaN-based high side switch configured to be connected between a voltage source and a switch-node;

a GaN-based low side switch configured to be connected between a ground and the switch-node;

a high side switch driver circuit having an output connected to the high side switch; and

a low side switch driver circuit having an output connected to the low side switch;

wherein the low side switch driver circuit is disposed on a silicon-based die that includes a control circuit configured to control the low side switch driver circuit and the high side switch driver circuit; and

a GaN-based level shift circuit configured receive a drive signal from the control circuit, level shift the drive signal and transmit a level shifted drive signal to the high side switch driver circuit.

11. The power conversion circuit of claim 10 further comprising a GaN-based bootstrap circuit.

12. The power conversion circuit of claim 10 further comprising a bootstrap circuit that includes a silicon-based bootstrap diode.

13. The power conversion circuit of claim 10 wherein the GaN-based low side switch is disposed on a first GaN-based die, the GaN-based high side switch is disposed on a second GaN-based die, the low side switch driver circuit is disposed on a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

14. The power conversion circuit of claim 10 wherein the high side switch driver circuit is disposed on a silicon-based die and includes a receiver circuit configured to receive the transmitted level shifted drive signal.

15. The power conversion circuit of claim 10 wherein the silicon-based die is a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.

16. A method of operating an electronic circuit, the method comprising:

controlling power delivered to a load with a synchronously operated GaN-based high side switch and a synchronously operated GaN-based low side switch;

supplying control signals to the GaN-based high side switch with a high side switch driver circuit; and

supplying control signals to the GaN-based low side switch with a low side switch driver circuit;

wherein the low side switch driver circuit is disposed on a silicon-based die that includes a control circuit configured to control the low side switch driver circuit and the high side switch driver circuit; and

a GaN-based level shift circuit configured receive a drive signal from the control circuit, level shift the drive signal and transmit a level shifted drive signal to the high side switch driver circuit.

17. The method of claim 16 wherein the GaN-based low side switch is disposed on a first GaN-based device, the GaN-based high side switch is disposed on a second GaN-based device, the low side switch driver circuit is disposed on a first silicon-based device and the high side switch driver circuit is disposed on a second silicon-based device.

18. The method of claim 17 wherein a GaN-based level shift circuit is disposed on a third GaN-based device.

19. The method of claim 16 wherein the high side switch driver circuit is disposed on a silicon-based die and includes a receiver circuit configured to receive the transmitted level shifted drive signal.

20. The method of claim 16 wherein the silicon-based die is a first silicon-based die and the high side switch driver circuit is disposed on a second silicon-based die.