High speed and high voltage driver
First Claim
1. A high speed high voltage (HSHV) open drain driver comprising:
- a main stack of N transistors of a first type coupled between a reference voltage and an output node of the HSHV driver, the N transistors comprising a first transistor as an input transistor of the HSHV open drain driver and an Nth transistor as an output transistor of the HSHV open drain driver, N being an integer equal to or greater than three;
a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of N−
1 transistors of a second type;
wherein;
a gate node of the first transistor of the main stack is coupled to a drain node of a first transistor of the biasing stack,gate nodes of a second to the (N−
1)th transistor of the main stack are coupled to respective N−
2 common source-drain nodes of the transistors of the biasing stack,a gate node of the Nth transistor of the main stack is coupled to a source node of the (N−
1)th transistor of the biasing stack,N−
1 common source-drain nodes of transistors of the main stack are coupled to respective N−
1 gate nodes of transistors of the biasing stack,the output node is a drain node of the output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, andtransistors of the main stack and the biasing stack have operating voltages substantially smaller than the high voltage.
0 Assignments
0 Petitions
Accused Products
Abstract
Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
16 Citations
22 Claims
-
1. A high speed high voltage (HSHV) open drain driver comprising:
-
a main stack of N transistors of a first type coupled between a reference voltage and an output node of the HSHV driver, the N transistors comprising a first transistor as an input transistor of the HSHV open drain driver and an Nth transistor as an output transistor of the HSHV open drain driver, N being an integer equal to or greater than three; a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of N−
1 transistors of a second type;wherein; a gate node of the first transistor of the main stack is coupled to a drain node of a first transistor of the biasing stack, gate nodes of a second to the (N−
1)th transistor of the main stack are coupled to respective N−
2 common source-drain nodes of the transistors of the biasing stack,a gate node of the Nth transistor of the main stack is coupled to a source node of the (N−
1)th transistor of the biasing stack,N−
1 common source-drain nodes of transistors of the main stack are coupled to respective N−
1 gate nodes of transistors of the biasing stack,the output node is a drain node of the output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and transistors of the main stack and the biasing stack have operating voltages substantially smaller than the high voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A high speed high voltage (HSHV) driver comprising:
-
a first stack of transistors of a first type coupled between a high voltage and an output node of the HSHV driver; a second stack of transistors of a second type opposite the first type coupled between the output node and a reference voltage; a first biasing circuit configured to provide biasing voltages to the first stack, the first biasing circuit comprising a first biasing stack of transistors of the second type; and a second biasing circuit configured to provide biasing voltages to the second stack, the second biasing circuit comprising a second biasing stack of transistors of the first type; wherein; transistors of each of the first stack, the first biasing stack, the second stack and the second biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor, a gate node of the first transistor of the first stack is configured to receive a level shifted version of the input signal, a gate node of the first transistor of the second stack is configured to receive the input signal, a source node of the first transistor of the first stack is coupled to the high voltage, a source node of the first transistor of the second stack is coupled to the reference voltage, a drain node of the last transistor of the first stack and a drain node of the last transistor of the second stack are coupled to the output node, gate nodes of a first to a last transistor of the first stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the first biasing stack, common source-drain nodes of the first to the last transistor of the first stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the first biasing stack, gate nodes of a first to a last transistor of the second stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the second biasing stack, common source-drain nodes of the first to the last transistor of the second stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the second biasing stack, the first biasing circuit further comprises a plurality of series connected resistors configured as a first resistive voltage divider between the high voltage coupled to the source node of the first transistor of the first stack and the output node coupled to the drain node of the last transistor of the first stack, where resistive nodes of the first resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the first stack in a one to one relationship, the second biasing circuit further comprises a plurality of series connected resistors configured as a second resistive voltage divider between the reference voltage coupled to the source node of the first transistor of the second stack and the output node coupled to the drain node of the last transistor of the second stack, where resistive nodes of the second resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the second stack in a one to one relationship, the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage, and transistors of the first stack, the second stack, the first biasing stack and the second biasing stack having desired operating voltages substantially smaller than the high voltage. - View Dependent Claims (22)
-
Specification