On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core

• US 10,171,081 B1
• Filed: 07/28/2017
• Issued: 01/01/2019
• Est. Priority Date: 07/28/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bose, Pradip, Buyuktosunoglu, Alper, Chuang, Pierce I-Jen, Restle, Phillip John, Vezyrtzis, Christos
• Primary Examiner(s): Le, Don
• Application Number:
  US15/663,033
• Time in Patent Office: 522 Days
• Field of Search: 326 27
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

Claims

1. A device, comprising:

a first voltage noise sensor located at a first unit of a processor core, wherein the first voltage noise sensor detects a first voltage droop at the first unit, and wherein the processor core is divided into the first unit and a second unit;

a global noise manager component located in the processor core and associated with a global control loop of the processor core, and that receives, from the first voltage noise sensor, an indication of the first voltage droop; and

a first local noise manager component located in the first unit and associated with a first local control loop of the first unit, where the first local noise manager component is distinct from the global noise manager component and;

receives, from the first voltage noise sensor, the indication of the first voltage droop; and

implements a first noise mitigation procedure at the first unit.

2. The device of claim 1, wherein the first voltage noise sensor digitally measures at least one of a power supply noise value or a slope at a determined voltage value.

3. The device of claim 1, wherein the first local noise manager component implements the first noise mitigation procedure over the first local control loop within the first unit, and wherein the first local noise manager component broadcasts information related to the first noise mitigation procedure of the first local control loop to the global noise manager component and to at least a second local noise manager component located in the second unit of the processor core.

4. The device of claim 3, wherein the global noise manager component implements a global noise mitigation procedure over the global control loop within the processor core, and wherein the first local control loop and the global control loop are independent loops.

5. The device of claim 4, wherein the first local control loop has a first reaction time with respect to the detection of the first voltage droop at the first unit that is faster than a second reaction time of the global control loop with respect to the detection of the first voltage droop at the first unit.

6. The device of claim 1, wherein the global noise manager component implements a global noise mitigation procedure based on a determination that the first voltage droop has continued for more than a defined number of cycles, and wherein the global noise mitigation procedure is applied at the first unit and the second unit of the processor core.

7. The device of claim 6, wherein the global noise mitigation procedure overrides the first noise mitigation procedure and the first local noise manager component discontinues implementation of the first noise mitigation procedure.

8. The device of claim 1, further comprising:

a second voltage noise sensor located at the second unit of the processor core and that detects a second voltage droop at the second unit; and

a second local noise manager component located in the second unit and that;

receives, from the second voltage noise sensor, a second indication of the second voltage droop; and

implements a second noise mitigation procedure at the second unit.

9. The device of claim 8, wherein the second local noise manager component implements the second noise mitigation procedure over a second local control loop within the second unit, and wherein the second local noise manager component broadcasts information related to the second noise mitigation procedure of the second local control loop to the global noise manager component and to the first local noise manager component.

10. The device of claim 1, wherein the first noise mitigation procedure implemented at the first unit increases a processing efficiency of the processor core.

11. The device of claim 1, further comprising a transmitter component that concurrently transmits the indication of the first voltage droop to the global noise manager component and the first local noise manager component.

12. The device of claim 8, further comprising a transmitter component that concurrently transmits the second indication of the second voltage droop to the global noise manager component and the second local noise manager component.

13. A computer program product that facilitates reduction of on-chip power supply noise, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions are executable by a processor core to cause the processor core to:

detect a first voltage droop at a first segment of the processor core;

transmit a first indication of the first voltage droop to a local noise management unit and a common noise management unit, wherein the local noise management unit is associated with the first segment of the processor core, the common noise management unit is associated with a global control loop of the processor core, and the local noise management unit is distinct from the common noise management unit and is associated with a local control loop of the first segment; and

execute a first sequence of instructions based on the first indication of the first voltage droop, and wherein the first sequence of instructions are received from the local noise management unit and relate to a mitigation countermeasure associated with the first voltage droop.

14. The computer program product of claim 13, wherein the program instructions are further executable by the processor core to cause the processor core to:

detect the first voltage droop or a second voltage droop at the first segment after an application of the first sequence of instructions at the first segment;

transmit a second indication of the first voltage droop or the second voltage droop to the local noise management unit and the common noise management unit; and

execute a second sequence of instructions at the first segment based on the second indication of the first voltage droop or the second voltage droop, and wherein the second sequence of instructions are received from the common noise management unit.

15. The computer program product of claim 13, wherein the second sequence of instructions overrides the first sequence of instructions at the first segment.

16. The computer program product of claim 13, wherein the program instructions are further executable by the processor core to cause the processor core to decouple a performance loss from the mitigation countermeasure from the detecting the first voltage droop.

17. The computer program product of claim 13, wherein the local noise management unit has a first reaction time with respect to the detection of the first voltage droop at the first segment of the processor core that is faster than a second reaction time of the common noise management unit with respect to the detection of the first voltage droop at the first segment of the processor core.

18. The computer program product of claim 14, wherein the second sequence of instructions are received from the common noise management unit based on a determination by the common noise management unit that the first voltage droop has continued for more than a defined number of cycles.

19. The computer program product of claim 13, wherein the processor core concurrently transmits the first indication of the first voltage droop to the global noise manager component and the first local noise manager component.

20. The computer program product of claim 13, wherein the processor core concurrently transmits the second indication of the second voltage droop to the global noise manager component and the second local noise manager component.