Sparse coding with Memristor networks

• US 10,171,084 B2
• Filed: 04/24/2018
• Issued: 01/01/2019
• Est. Priority Date: 04/24/2017
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Lu, Wei, Cai, Fuxi, Sheridan, Patrick, Du, Chao
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US15/960,772
• Publication Number:
  US 20180309451A1
• Time in Patent Office: 252 Days
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06N 3/02 Neural networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04Q 11/00 Selecting arrangements for multiplex systems multiplex systems H04J
• CPC Class Codes: H04Q 3/0004 using crossbar selectors in the switching stages

Abstract

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

Claims

1. A system for sparse coding with an array of resistive memory devices, comprising:

an array of resistive memory devices arranged in columns and rows to form a matrix, wherein each column represents a potential feature of an input;

an interface circuit electrically coupled to the matrix, wherein the interface circuit cooperatively operates with the array of resistive memory devices to perform computing in the array of resistive memory devices, wherein the interface circuit controls a computation of;

(a) a first dot product operation by feeding an input vector forward through the matrix to yield an output vector, where the input vector is a column vector with each element representing intensity of a pixel in an image and the output vector is row vector with each element representing the dot product between the input vector and a feature vector stored in a corresponding column of the matrix;

(b) a second dot product operation by feeding a neuron activity vector backward through the matrix to yield an intermediate result vector, where the neuron activity vector is a row vector representing a level of activity from all of the neurons in the matrix and the intermediate result vector is a column vector;

(c) a new input vector by subtracting the intermediate result vector from the input vector; and

(d) a third dot product operation by feeding the new input vector forward through the matrix to yield a new output vector, where the output vector is a row vector with each element representing the dot product between the input vector and the feature vector stored in the corresponding column of the matrix.

2. The system of claim 1 wherein the interface circuit applies elements of the output vector to the matrix and uses the output vector as the neuron activity vector according to a sparse coding algorithm.

3. The system of claim 1 wherein the interface circuit evaluates each element of the output vector in relation to a threshold and sets a value of each element in the neuron activity vector to zero when the value of the given element is less than the threshold.

4. The system of claim 3 wherein the interface circuit evaluates each element of the output vector in relation to a threshold and sets a value of each element in the neuron activity vector to a value of the corresponding element of the output vector when the value of the given element is greater than the threshold.

5. The system of claim 1 wherein the interface circuit performs neuromorphic computing in accordance with a locally competitive algorithm.

6. The system of claim 1 wherein the interface circuit iteratively performs steps (b)-(d) for a fixed number of iterations.

7. The system of claim 6 wherein the interface circuit includes a counter, and wherein the counter is configured to maintain a count of iterations that indicates a number of iterations performed.

8. The system of claim 1 wherein values of the elements in the input vector are represented by voltages applied to the matrix, where the voltage is applied as pulses having a fixed amplitude and a duration proportional to the corresponding value.

9. The system of claim 1 wherein the intermediate result vector represents a reconstruction of the input.

10. The system of claim 1 wherein each data value in the array of resistive memory devices stores at least one of a resistance and a conductance, and wherein at least one of the resistance and the conductance is an element of potential feature represented in the column.

11. An interface circuit storing processor-executable instructions for sparse coding with an array of resistive memory devices arranged in columns and rows to form a matrix, the instructions comprising:

(a) computing a first dot product operation by feeding an input vector forward through a matrix to yield an output vector, where the input vector is a column vector with each element representing intensity of a pixel in an image and the output vector is row vector with each element representing the dot product between the input vector and a feature vector stored in a corresponding column of the matrix;

(b) computing a second dot product operation by feeding a neuron activity vector backward through the matrix to yield an intermediate result vector, where the neuron activity vector is a row vector representing a level of activity from all of the neurons in the matrix and the intermediate result vector is a column vector;

(c) computing a new input vector by subtracting the intermediate result vector from the input vector; and

(d) computing a third dot product operation by feeding the new input vector forward through the matrix to yield a new output vector, where the output vector is a row vector with each element representing the dot product between the input vector and the feature vector stored in the corresponding column of the matrix.

12. The interface circuit of claim 11 wherein the instructions include applying elements of the output vector to the matrix and using the output vector as the neuron activity vector according to a sparse coding algorithm.

13. The interface circuit of claim 11 wherein the instructions include evaluating each element of the output vector in relation to a threshold and setting a value of each element in the neuron activity vector to zero when the value of the given element is less than the threshold.

14. The interface circuit of claim 13 wherein the instructions include evaluating each element of the output vector in relation to a threshold and setting a value of each element in the neuron activity vector to a value of the corresponding element of the output vector when the value of the given element is greater than the threshold.

15. The interface circuit of claim 11 wherein the instructions include performing neuromorphic computing in accordance with a locally competitive algorithm.

16. The interface circuit of claim 11 wherein the instructions include iteratively performing steps (b)-(d) for a fixed number of iterations.

17. The interface circuit of claim 16 further comprising a counter, wherein the counter is configured to maintain a count of iterations that indicates a number of iterations performed.

18. The interface circuit of claim 11 wherein values of the elements in the input vector are represented by voltages applied to the matrix, where the voltage is applied as pulses have a fixed amplitude and a duration proportional to the corresponding value.

19. The interface circuit of claim 11 wherein the intermediate result vector represents a reconstruction of the input.

20. The interface circuit of claim 11 wherein each data value in the array of resistive memory devices stores at least one of a resistance and a conductance, and wherein at least one of the resistance and the conductance is an element of potential feature represented in the column.