Methods and apparatus for control bit detection

• US 10,171,207 B2
• Filed: 04/26/2017
• Issued: 01/01/2019
• Est. Priority Date: 04/26/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Ren, Tianmin
• Primary Examiner(s): Perez, James M
• Application Number:
  US15/498,373
• Publication Number:
  US 20180316463A1
• Time in Patent Office: 615 Days
• Field of Search: 375259-285, 375316-352
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 1/1607 Details of the supervisory signal
• CPC Class Codes: H04L 5/0053 Allocation of signaling, i.e. of overhead other than pilot signals
• CPC Class Codes: H04W 24/02 Arrangements for optimising operational condition
• CPC Class Codes: H04W 24/10 Scheduling measurement reports ; Arrangements for measurement reports
• CPC Class Codes: H04W 72/21 in the uplink direction of a wireless link, i.e. towards the network

Abstract

Methods and apparatus for control bit detection. In an exemplary embodiment, a method includes receiving an LLR sequence (l) that includes P control bits and calculating a sum of LLR squares parameter (L) associated with the LLR sequence. The method also includes generating a value (Vp) for each of the 2^P combination of the control bits. Each Vp value is based on a parameter sequence and the LLR sequence. The method also includes determining a smallest value of Vp, and outputting a determination that a control bit combination was received if the smallest value of Vp is less than a threshold value (THD) multiplied by the parameter L.

Claims

1. A method of detecting control bit information from a user equipment (UE) via a communication network which includes at least one radio tower, switching network, and a control bit detector (CBD), wherein the CBD includes a threshold generator, a control bit log-likelihood ratio (LLR) input interface, a processor, and an output register, the method comprising:

receiving, at the control bit LLR input interface, an LLR sequence (l) that includes P control bits;

calculating, at the processor, a sum of LLR squares parameter (L) associated with the LLR sequence;

generating a (Vp) value for each of 2^P combinations of the control bits, wherein each Vp value is computed based on a new sequence and the LLR sequence;

determining, by the processor, a smallest value of Vp; and

outputting, by the CBD, a determination that a control bit combination was received if the smallest value of Vp is less than a threshold value (THD) multiplied by the parameter L.

2. The method of claim 1, further comprising pre-calculating the threshold value based on a value N and a target false alarm probability (FAP) value.

3. The method of claim 1, further comprising generating the value Vp based on an average of absolute values (lavg) of the LLR sequence.

4. The method of claim 3, further comprising calculating (lavg) according to

5. The method of claim 3, wherein the operation of generating the Vp value for each of the 2^P combinations of the control bits comprises:

for each of the 2^P combinations of the control bits, performing operations of;

generating a scrambling sequence u(p) corresponding to a selected combination of the control bits;

calculating the new sequence from an element-wise product stream based on u(p) and l; and

calculating the Vp value from the new sequence and the lavg.

6. The method of claim 5, wherein the operation of generating the scrambling sequence u(p) comprises generating the scrambling sequence u(p) according to u(p)=(u₀^p, u₁^p, . . . u_N-1^p).

7. The method of claim 5, wherein the operation of calculating the new sequence comprises calculating the new sequence according to (s₀^p, s₁^p, . . . s_N-1^p)=(l₀(1−

2u₀^p),l₁(1−

2u₁^p), . . . l_N-1(1−

2u_N-1^p)).

8. The method of claim 5, wherein the operation of calculating the values of Vp comprises calculating the values of Vp according to

9. The method of claim 5, wherein each element of the scrambling sequence u(p) is either one or zero.

10. The method of claim 1, further comprising outputting a did not transmit (DTX) determination if the smallest value of Vp is not less than the threshold multiplied by L.

11. The method of claim 1, further comprising receiving the LLR sequence in a subframe of symbols in an uplink transmission from user equipment (UE).

12. The method of claim 11, wherein the uplink transmission comprises an LTE uplink transmission.

13. The method of claim 11, wherein the uplink transmission is received over a physical uplink shared channel (PUSCH).

14. An apparatus configured to detect control bit information from a user equipment (UE) via a communication network which includes at least one radio tower, a switching network, and a transceiver containing a receiver portion, wherein the receiver portion includes a control bit detector (CBD), the CBD comprising:

a control bit log-likelihood ratio (LLR) input interface configured to receive an LLR sequence (l) that includes P control bits from the UE;

a processor coupled to the control bit LLR input interface that performs operations of;

calculating a sum of LLR squares parameter (L) associated with the LLR sequence;

generating a (Vp) value for each of 2^P combinations of the control bits, wherein each Vp value is based on a new sequence and the LLR sequence; and

determining a smallest value of Vp; and

an output interface coupled to the processor configured to output a determination that a control bit combination was received if the smallest value of Vp is less than a threshold value (THD) multiplied by the parameter L.

15. The apparatus of claim 14, wherein the processor performs an operation of calculating an average of absolute values (lavg) of the LLR sequence.

16. The apparatus of claim 14, wherein the processor performs an operation of calculating (lavg) according to

17. The apparatus of claim 14, wherein the operation of generating comprises:

for each of the 2^P combinations of the control bits, performing operations of;

generating a scrambling sequence u(p) corresponding to a selected combination of the control bits;

calculating the new sequence from an element-wise product stream based on u(p) and l; and

calculating the Vp value from the new sequence and an average of absolute values (lavg) of the LLR sequence.

18. The apparatus of claim 17, wherein the operation of generating the scrambling sequence comprises generating the scrambling sequence u(p) according to u(p)=(u₀^p, u₁^p, . . . u_N-1^p).

19. The apparatus of claim 17, wherein the operation of calculating the new sequence comprises calculating the new sequence according to (s₀^p, s₁^p, . . . s_N-1^p)=(l₀(1−

2u₀^p),l₁(1−

2u₁^p), . . . l_N-1(1−

2u_N-1^p)).

20. The apparatus of claim 17, wherein the operation of calculating the Vp value comprises calculating the Vp value according to