Interfaces for selecting among multiple communications protocols

• US 10,171,633 B2
• Filed: 03/09/2017
• Issued: 01/01/2019
• Est. Priority Date: 03/09/2017
• Status: Active Grant

• Current Assignee: Astronics Advanced Electronic Systems Corporation (Astronics Corporation)
• Original Assignee: Astronics Advanced Electronic Systems Corporation (Astronics Corporation)
• Inventors: Perchlik, David
• Primary Examiner(s): Jangbahadur, Lakeram
• Application Number:
  US15/454,869
• Publication Number:
  US 20180262595A1
• Time in Patent Office: 663 Days
• CPC Class Codes: H04B 7/18502 Airborne stations
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/40169 Flexible bus arrangements arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654
• CPC Class Codes: H04L 2012/4028 the transportation system being an aircraft
• CPC Class Codes: H04L 69/03 Protocol definition or specification protocol conformance testing H04L1/244

Abstract

Interface circuits are disclosed for manually or automatically selecting among two or more communications protocols in ways that reduce the number of connector pins needed and/or use the same number of connector pins required for a single communications protocol. Such interface circuits are advantageously applicable to selecting and accommodating either RS-485 or 802bw communications protocols in aircraft electronics while enabling space and cost efficient designs.

Claims

1. An interface circuit for selecting and processing signals corresponding to one of a plurality of communications protocols provided on one or more communications ports, comprising:

a processor;

an Ethernet switch in electronic communication with the processor;

a plurality of physical layer circuits, each in electronic communication with the Ethernet switch and each including a RS-485 transceiver and capable of transmitting and receiving each of 802.3bw Ethernet signals and RS-485 signals;

wherein each physical layer circuit has two associated pins;

wherein the processor is configured to

determine on each of the physical layer circuits that an incoming communication is one of a 802.3bw Ethernet communication and an RS-485 communication by detecting at last one of 1. that the width of at least one data pulse of the incoming communication is greater than the range defined by the 802.3bw protocol, and 2. that an RS-485 or 802.3bw preamble is present in the incoming communication,

and the processor is further configured to, when the incoming communication is an RS-485 communication, send a command to the Ethernet switch and the physical layer circuit receiving the RS-485 communication that a RS-485 mode is to be employed, wherein in RS-485 mode the Ethernet switch retransmits serial data or,

when the incoming communication is an 802.3bw Ethernet communication, send a command to the 802.3bw Ethernet switch and the physical layer circuit receiving the Ethernet communication that a 802.3bw Ethernet mode is to be employed.

2. An interface circuit for selecting and processing signals on one or more ports corresponding to either an RS-485 or 802.3bw Ethernet protocol, comprising:

a processor,

at least one port;

each port having associated with and in communication with RS-485 signal processing circuitry and 802.3bw Ethernet signal processing circuitry;

wherein the RS-485 signal processing circuitry and 802.3bw Ethernet signal processing circuitry includes one or more physical layer circuits (PHYs), each PHY connected to one of the at least one ports, and having an RS-485 transceiver;

wherein the processor is configured to;

determine whether the ports are receiving RS-485 signals or 802.3bw Ethernet signals by detecting at least one of 1. that the width of at least one data pulses of a communication is greater than the range defined by the 802.3bw protocol, and 2. that an RS-485 or 802.3bw preamble is present in the communication,

and to process communications with the ports according to which of RS-485 signals or 802.3bw Ethernet is being received.

3. The interface circuit of claim 2 further comprising an Ethernet switch coupled between the processor and the one or more PHYs.

4. The interface circuit of claim 3 further comprising a media access controller/network interface controller (MAC/NIC) coupled between the Ethernet switch and the processor.

5. An interface circuit for selecting and processing signals corresponding to either an RS-485 or 802.3bw Ethernet protocol, comprising:

at least one port, each port configured to receive both RS-485 communications and 802.3bw Ethernet communications;

a processor;

RS-485 signal processing circuitry coupled to the processor;

802.3bw Ethernet signal processing circuitry coupled to the processor; and

wherein the processor detects if signals input on each port correspond to the RS-485 protocol or the 802.3bw Ethernet protocol by detecting at least one of 1. that the width of at least one data pulse of the signals input on each port is greater than the range defined by the 802.3bw protocol, and 2. that an RS-485 or 802.3bw preamble is present in the signals input on each port, and route the signals between each port and one of the RS-485 or 802.3bw Ethernet signal processing circuitry to match the protocol of the signals to their appropriate signal processing circuitry.

6. The interface circuit of claim 5, wherein the output of the RS-485 or 802.3bw Ethernet processing circuitry is provided from each port to a shared two wire bus.

7. The interface circuit of claim 5, wherein the RS-485 signal processing circuitry or 802.3bw Ethernet processing circuitry to which signals are not routed by the processor is turned off to reduce power consumption.

8. An interface circuit for selecting and processing signals corresponding to either an RS-485 or 802.3bw Ethernet protocol on one or more ports, comprising:

at least one port configured to receive both RS-485 communications and 802.3bw Ethernet communications;

a processor;

a switch coupled to the processor, the switch including circuitry for detecting if signals received thereby from each port comply with RS-485 protocol or 802.3bw Ethernet protocol by detecting at least one of 1. that the width of at least one data pulse of the signals input on each port is greater than the range defined by the 802.3bw protocol, and 2. that an RS-485 or 802.3bw preamble is present in the signals input on each port; and

a physical layer circuit coupled between the switch and each port configured to process signals provided in either RS-485 or 802.3bw protocol as detected by the switch.

9. The interface circuit of claim 8, wherein the signals after processing are output from each port on a shared two wire bus.