Apparatus for receiver with multi-bit observation interval and associated methods

• US 10,172,105 B2
• Filed: 05/25/2016
• Issued: 01/01/2019
• Est. Priority Date: 07/24/2013
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: de Ruijter, Hendricus, Xiong, Ping, Li, Wentao
• Primary Examiner(s): Roberts, Brian S
• Application Number:
  US15/164,363
• Publication Number:
  US 20160353398A1
• Time in Patent Office: 951 Days
• Field of Search: None
• CPC Class Codes: H04J 3/1605 Fixed allocated frame structures
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 43/028 by filtering
• CPC Class Codes: H04W 4/70 Services for machine-to-machine communication [M2M] or machine type communication [MTC]
• CPC Class Codes: H04W 56/001 Synchronization between nodes
• CPC Class Codes: H04W 74/0833 Random access procedures, e.g. with 4-step access

Abstract

An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.

Claims

1. An apparatus, comprising:

a radio frequency (RF) receiver having a multi-bit observation interval, the RF receiver comprising a;

a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal;

a timing correlator and frequency offset estimator circuit coupled to receive data derived from a frequency signal derived from the phase signal; and

a Viterbi decoder circuit coupled to provide decoded data derived from the frequency signal.

2. The apparatus according to claim 1, further comprising a phase differentiator circuit to differentiate the phase signal and to provide a frequency signal.

3. The apparatus according to claim 2, further comprising a random access memory circuit to receive the frequency signal.

4. The apparatus according to claim 3, further comprising an adder circuit to add data from the random access memory circuit to a frequency offset estimate to generate a sum and to provide the sum to the timing correlator and frequency offset estimator circuit.

5. The apparatus according to claim 4, wherein the frequency offset estimate comprises an initial frequency offset estimate provided by an initial frequency offset estimator circuit.

6. The apparatus according to claim 4, wherein the frequency offset estimate comprises a frequency offset estimate provided by the timing correlator and frequency offset estimator circuit.

7. The apparatus according to claim 1, wherein a feedback signal is used by the timing correlator and frequency offset estimator circuit to perform a timing estimation operation or a frequency offset estimate operation for tracking of timing or frequency drift, respectively.

8. The apparatus according to claim 1, wherein the timing correlator and frequency offset estimator circuit selectively performs at least one of:

(a) initial timing detection, (b) frequency offset estimation, (c) timing tracking, and (d) frequency offset tracking.

9. The apparatus according to claim 1, further comprising a signal arrival detector circuit to detect arrival of the RF signals, wherein the timing correlator and frequency offset estimator circuit operates in response to the detection of the arrival of the RF signals.

10. An integrated circuit (IC), comprising:

a radio frequency (RF) receiver, comprising;

a Coordinate Rotation Digital Computer (Cordic) circuit to receive in-phase and quadrature signals derived from RF signals and to generate phase and amplitude signals;

a signal arrival detector circuit to use the phase and amplitude signals to detect arrival of an RF signal and to provide a signal detect output signal; and

a timing correlator and frequency offset estimator circuit coupled to receive a frequency signal derived from the phase signal to selectively perform at least one of;

(a) initial timing detection, (b) frequency offset estimation, (c) timing tracking, and (d) frequency offset tracking.

11. The IC according to claim 10, further comprising:

an initial frequency offset estimator circuit to provide an initial frequency offset estimate; and

an adder circuit to add the initial frequency offset estimate to a frequency offset estimate from the timing correlator and frequency offset estimator circuit.

12. The IC according to claim 11, further comprising:

a phase differentiator circuit to receive the phase signal and to provide a frequency signal;

a memory circuit to receive and store the frequency signal and to provide the stored signal to the adder circuit in response to an address signal;

a controller circuit to generate the address signal based on at least one of;

(a) signal detect output signal, (b) timing correlator output of the timing correlator and frequency offset estimator circuit; and

a Viterbi decoder circuit to provide decoded signals derived from adder output.

13. The IC according to claim 10, wherein the timing correlator and frequency offset estimator comprises:

a shift register circuit having a plurality of register circuits to receive a frequency signal;

a plurality of subtractor circuits to subtract a plurality of coefficients from corresponding signals from the plurality of register circuits of the shift register circuit to generate a plurality of difference signals; and

a plurality of absolute value circuits to selectively provide as output signals either the plurality of difference signals or absolute values of plurality of difference signals.

14. The IC according to claim 13, wherein the timing correlator and frequency offset estimator circuit further comprises:

an adder circuit to provide a sum of the output signals of the plurality of absolute value circuits; and

a demultiplexer circuit to provide, in response to a control signal, either the sum of the output signals of the plurality of absolute value circuits or a divided value of the sum of the output signals of the plurality of absolute value circuits.

15. A method of receiving radio frequency (RF) signals, the method comprising:

receiving time domain signals derived from the RF signals in a Coordinate Rotation Digital Computer (Cordic) circuit and generating a phase signal;

using a timing correlator and frequency offset estimator to provide at least one of initial timing detection, frequency offset estimation, timing tracking, and frequency offset tracking using data derived from a frequency signal derived from the phase signal; and

decoding, using a Viterbi decoder, data derived from the frequency signal.

16. The method according to claim 15, further comprising:

phase differentiating the phase signal and providing a frequency signal; and

storing in a memory the data related to the frequency signal.

17. The method according to claim 16, further comprising adding data stored in the memory to a frequency offset estimate to generate a sum and providing the sum to the timing correlator and frequency offset estimator.

18. The method according to claim 17, wherein the frequency offset estimate comprises an initial frequency offset estimate provided by an initial frequency offset estimator, or a frequency offset estimate provided by the timing correlator and frequency offset estimator.

19. The method according to claim 15, further comprising using the feedback signal by the timing correlator and frequency offset estimator to perform a timing tracking operation or a frequency offset estimate operation to compensate for timing or frequency drift, respectively.

20. The method according to claim 19, wherein the feedback signal is derived from the decoded data provided by the Viterbi decoder.