Compensated low dropout with high power supply rejection ratio and short circuit protection

• US 10,175,706 B2
• Filed: 06/17/2016
• Issued: 01/08/2019
• Est. Priority Date: 06/17/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Golara, Soheil, Vakili-Amini, Babak
• Primary Examiner(s): Zhang, Jue
• Application Number:
  US15/186,411
• Publication Number:
  US 20170364110A1
• Time in Patent Office: 935 Days
• CPC Class Codes: G05F 1/573 with overcurrent detector
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

Disclosed is a low dropout (LDO) voltage regulator that includes a differential amplifier configured to amplify a differential between a reference voltage and a regulated output voltage, a pass transistor coupled to the differential amplifier and driven by an output of the differential amplifier, a compensation capacitor coupled to an output node of the differential amplifier, and an auxiliary amplifier, wherein an output node of the auxiliary amplifier is coupled to the compensation capacitor, and wherein an input node of the auxiliary amplifier is coupled to the pass transistor.

Claims

1. A low dropout (LDO) voltage regulator, comprising:

a differential amplifier configured to amplify a differential between a reference voltage and a regulated output voltage;

a PMOS (P-channel Metal Oxide Semiconductor) pass transistor coupled to the differential amplifier and driven by an output of the differential amplifier;

a compensation capacitor coupled to an output node of the differential amplifier; and

an auxiliary amplifier comprising a low current open loop differential amplifier having a low current comprising 25 nano amps, wherein an output node of the auxiliary amplifier is coupled to the compensation capacitor, and wherein an input node of the auxiliary amplifier is coupled to the PMOS pass transistor.

2. The LDO voltage regulator of claim 1, wherein compensation of the compensation capacitor is increased based on an amount of gain provided by the auxiliary amplifier.

3. The LDO voltage regulator of claim 2, wherein the compensation of the compensation capacitor stabilizes a circuit containing the LDO voltage regulator.

4. The LDO voltage regulator of claim 1, wherein a power supply rejection ratio (PSRR) of a circuit containing the LDO voltage regulator improves based on an amount of gain provided by the auxiliary amplifier.

5. The LDO voltage regulator of claim 1, wherein the LDO voltage regulator utilizes Miller compensation.

6. The LDO voltage regulator of claim 5, wherein the auxiliary amplifier includes a resistive load that limits an amount of gain of the auxiliary amplifier.

7. The LDO voltage regulator of claim 1, wherein the LDO voltage regulator comprises a closed loop operational amplifier.

8. The LDO voltage regulator of claim 1, further comprising:

an active clamp coupled to the output node of the differential amplifier and the PMOS pass transistor.

9. The LDO voltage regulator of claim 8, wherein the active clamp limits short-circuit current surges from the PMOS pass transistor.

10. The LDO voltage regulator of claim 8, wherein the PMOS pass transistor receives a voltage of 2V to 3.6V from a battery, and wherein the LDO voltage regulator supplies an off-chip load capacitor with a voltage of 1.8V.

11. A method for compensating a low dropout (LDO) voltage regulator, comprising:

amplifying, by a differential amplifier, a differential between a reference voltage and a regulated output voltage;

receiving, at a PMOS pass transistor coupled to the differential amplifier, an output of the differential amplifier;

receiving, at a compensation capacitor, an output signal from an auxiliary amplifier, the auxiliary amplifier comprising a low current open loop differential amplifier having a low current comprising 25 nano-amps wherein the low current comprises a current of 25 nano amps, wherein the compensation capacitor is coupled to an output node of the differential amplifier, wherein an output node of the auxiliary amplifier is coupled to the compensation capacitor, and wherein an input node of the auxiliary amplifier is coupled to the PMOS pass transistor.

12. The method of claim 11, wherein the output signal from the auxiliary amplifier causes compensation of the compensation capacitor to increase based on an amount of gain provided by an input signal from the auxiliary amplifier.

13. The method of claim 12, wherein the compensation of the compensation capacitor stabilizes a circuit containing the LDO voltage regulator.

14. The method of claim 11, wherein a power supply rejection ratio (PSRR) of a circuit containing the LDO voltage regulator improves based on an amount of gain provided by the auxiliary amplifier.

15. The method of claim 11, wherein the LDO voltage regulator utilizes Miller compensation.

16. The method of claim 11, wherein the auxiliary amplifier includes a resistive load that limits an amount of gain of the auxiliary amplifier.

17. The method of claim 11, wherein the LDO voltage regulator comprises a closed loop operational amplifier.

18. The method of claim 11, further comprising:

coupling an active clamp to the output node of the differential amplifier and the PMOS pass transistor.

19. The method of claim 18, wherein the active clamp limits short-circuit current surges from the PMOS pass transistor.

20. The method of claim 18, wherein the PMOS pass transistor receives a voltage of 2V to 3.6V from a battery, and wherein the LDO voltage regulator supplies an off-chip load capacitor with a voltage of 1.8V.

21. An apparatus for compensating a low dropout (LDO) voltage regulator, comprising:

a differential amplifier configured to amplify a differential between a reference voltage and a regulated output voltage;

a PMOS pass transistor coupled to the differential amplifier and driven by an output of the differential amplifier;

a compensation means coupled to an output node of the differential amplifier; and

an auxiliary low current open loop differential amplification means amplifier having a low current comprising 25 nano amps, wherein an output node of the auxiliary amplification means is coupled to the compensation means, and wherein an input node of the auxiliary amplification means is coupled to the PMOS pass transistor.

22. The apparatus of claim 21, wherein compensation of the compensation means is increased based on an amount of gain provided by the auxiliary amplification means.

23. The apparatus of claim 21, wherein a power supply rejection ratio (PSRR) of a circuit containing the LDO voltage regulator improves based on an amount of gain provided by the auxiliary amplification means.

24. A low dropout (LDO) voltage regulator, comprising:

a differential amplifier configured to amplify a differential between a reference voltage and a regulated output voltage;

a PMOS (P-channel Metal Oxide Semiconductor) pass transistor coupled to the differential amplifier and driven by an output of the differential amplifier;

a compensation capacitor coupled to an output node of the differential amplifier; and

an auxiliary amplifier comprising a low current open loop differential amplifier, wherein an output node of the auxiliary amplifier is coupled to the compensation capacitor, and wherein an input node of the auxiliary amplifier is coupled to the PMOS pass transistor, wherein the differential amplifier uses a low bias current provided by a bandgap current source.