Domain-differentiated power state coordination system
First Claim
1. A multi-core microprocessor with an inter-core operating state coordination system, the microprocessor comprising:
- a plurality of cores configured to coordinate with each other in a structured hierarchical manner, each having its own independently settable target operating state selected from a plurality of possible target operating states designating configurations for local resources that are used only by the core, group resources that are used by multiple cores but not all of the cores, and global resources that are used by all of the cores;
a plurality of resource-associated domains including core domains, group domains, and a global domain, wherein a core domain corresponds to a single core and the local resources used only by that single core, a group domain corresponds to multiple cores and the group resources that they share, and a global domain corresponds to all of the cores and the global resources they share;
coordination logic provided exclusively on each of the plurality of the cores, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination, the coordination logic being configured to implement the core'"'"'s target operating state only to the extent that implementation of the target operating state would not reduce performance of any other core in the hierarchy below the target operating state of the any other core.
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Abstract
A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core'"'"'s target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.
80 Citations
20 Claims
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1. A multi-core microprocessor with an inter-core operating state coordination system, the microprocessor comprising:
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a plurality of cores configured to coordinate with each other in a structured hierarchical manner, each having its own independently settable target operating state selected from a plurality of possible target operating states designating configurations for local resources that are used only by the core, group resources that are used by multiple cores but not all of the cores, and global resources that are used by all of the cores; a plurality of resource-associated domains including core domains, group domains, and a global domain, wherein a core domain corresponds to a single core and the local resources used only by that single core, a group domain corresponds to multiple cores and the group resources that they share, and a global domain corresponds to all of the cores and the global resources they share; coordination logic provided exclusively on each of the plurality of the cores, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination, the coordination logic being configured to implement the core'"'"'s target operating state only to the extent that implementation of the target operating state would not reduce performance of any other core in the hierarchy below the target operating state of the any other core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of managing power consumption in a multi-core microprocessor, wherein a plurality of cores configured to coordinate with each other in a structured hierarchical manner, each have an independently settable target operating state selected from a plurality of possible target operating states designating configurations for local resources that are used only by the core, group resources that are used by multiple cores but not all of the cores, and global resources that are used by all of the cores;
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wherein the cores are hierarchically organized into a plurality of resource-associated domains including core domains, group domains, and a global domain; wherein a core domain corresponds to a single core and the local resources used only by that single core, a group domain corresponds to multiple cores and the group resources that they share, and a global domain corresponds to all of the cores and the global resources they share; the method comprising; an originating core receiving an instruction setting its target operating state; and the originating core, in response to the instruction, executing coordination logic provided exclusively on the originating core, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination and configured to implement the target operating state only to the extent that implementation of the target operating state would not reduce performance of any other core in the hierarchy below the target operating state of the any other core. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method of managing power consumption in a multi-core microprocessor, the method comprising:
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an operating system providing each of a plurality of cores, configured to coordinate with each other in a structured hierarchical manner, one of a plurality of independently settable target operating states, wherein each target operating state provides for a configuration of one or more local resources and one or more group resources, wherein a local resource is a resource used by only one core and a group resource is used by a group of cores; each core implementing the configurations of the one or more local resources set forth in its own target operating state; each core initiating a first discovery process to discover whether implementation of any configuration of any group resource in accordance with its own target operating state would reduce performance of any other core sharing the group resource hierarchically below the other core'"'"'s target operating state; and each core executing coordination logic provided exclusively on the core, the coordination logic being operable to receive a target operating state and initiate a composite operating state discovery process that includes inter-core coordination, to implement any configuration of any group resource in accordance with its own target operating state only to the extent to which it would not reduce performance of any other core sharing the group resource below the other core'"'"'s target operating state. - View Dependent Claims (19, 20)
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Specification