Memory device managing data in accordance with command and non-transitory computer readable recording medium

• US 10,175,885 B2
• Filed: 01/19/2016
• Issued: 01/08/2019
• Est. Priority Date: 01/19/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kanno, Shinichi, Nishimura, Hiroshi, Yoshida, Hideki
• Primary Examiner(s): Tsai, Sheng Jen
• Application Number:
  US15/000,627
• Publication Number:
  US 20160210052A1
• Time in Patent Office: 1,085 Days
• Field of Search: 711103
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.

Claims

1. A memory device comprising:

a nonvolatile memory; and

a controller controlling the nonvolatile memory, wherein

the controller comprises first to third processors,

the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and determines the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, and

the controller determines, based on priority information including priority degrees associated with the new processing, at least one of the new processing that has an execution destination determined by the first processor to be executed next by one of the second and third processors.

4. The memory device of claim 1, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages the processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module, and

the program refers to the priority information, and determines the new processing whose management destination is changed from the first management module to one of the second and third management modules.

5. The memory device of claim 1, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module,

the program refers to the priority information including priority degrees associated with new processing managed by the second management module, and determines processing executed subsequently among the processing managed by the second management module, and

the program refers to the priority information including priority degrees associated with new processing managed by the third management module, and determines processing executed subsequently among the processing managed by the third management module.

2. A memory device comprising:

a nonvolatile memory; and

a controller controlling the nonvolatile memory, wherein

the controller comprises first to third processors,

the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and determines the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, and

the second processor determines, whether processing executed by the second processor has a dependence that next processing activated subsequent to the processing executed by the second processor is to be executed by the second processor, and, when the processing executed by the second processor has the dependence, the second processor determines that the next processing is to be executed by the second processor.

6. The memory device of claim 2, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module,

if the next processing is to be executed by the second processor, the program manages the next processing using the second management module, and

if the next processing is executable by any one of the second and third processors, the program manages the next processing using the first management module.

7. The memory device of claim 2, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module,

if the next processing is to be executed by the second processor, the program manages the next processing using the second management module,

if the next processing is executable by any one of the second and third processors, and if the number of processing managed by the second management module is not more than the first threshold, the program manages the next processing using the second management module, if the next processing is executable by any one of the second and third processors, and if the number of processing managed by the third management module is not more than the second threshold, the program manages the next processing using the third management module, and

if the number of processing managed by the second management module is more than the first threshold, and if the number of processing managed by the third management module is more than the second threshold, the program manages the next processing using the first management module.

3. A memory device comprising:

a nonvolatile memory; and

a controller controlling the nonvolatile memory, wherein

the controller comprises first to third processors,

the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, and

the controller further comprises a shared memory shared among the first to third processor, and allocates, to processing before execution, a memory area in the shared memory used for the processing before execution.

8. The memory device of claim 3, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module.

9. The memory device of claim 3, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module, and

the program manages processing associated with hardware identification information indicating part of the controller, using a management module corresponding to the hardware identification information among the first to third management modules.

10. The memory device of claim 3, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages the processing to be executed by the second processor and execution order of the processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages the processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new processing managed by the first management module from the first management module to the third management module,

first processing is executed by any one of the second and third processors,

second processing is executed by any one of the second and third processors after execution of the first processing, and

the first processing notifies the second processing of area information of at least part of the memory area in the shared memory, if the at least part of the memory area used for the first processing is used for the second processing.

11. The memory device of claim 3, further comprising a storage unit storing a program which controls the controller if the program is executed by the controller, wherein

the first to third processors are controlled by the program,

the controller comprises:

a first management module which corresponds to the first processor, and manages the new processing and execution order of the new processing;

a second management module which corresponds to the second processor, and manages the processing to be executed by the second processor and execution order of processing to be executed by the second processor; and

a third management module which corresponds to the third processor, and manages processing to be executed by the third processor and execution order of the processing to be executed by the third processor,

if the number of processing managed by the second management module is not more than the first threshold, the program changes a management destination of the new processing managed by the first management module from the first management module to the second management module,

if the number of processing managed by the third management module is not more than the second threshold, the program changes the management destination of the new waiting processing managed by the first management module from the first management module to the third management module,

first processing is executed by any one of the second and third processors,

second processing is executed by any one of the second and third processors after execution of the first processing,

third processing is executed by any one of the second and third processors after execution of the second processing, and

the second processing receives, from the first processing, identification information indicating at least one of the first and third processing, reads information used for the second processing from a first memory area of the shared memory corresponding to the at least one of the first and third processing, and stores a result of execution of the second processing in a second memory area corresponding to the at least one of the first and third processing.

12. The memory device of claim 11, wherein the second processing reads information used for the second processing from a memory area corresponding to the first processing, and stores a result of execution of the second processing in a memory area corresponding to the third processing.

13. A memory device comprising:

a nonvolatile memory; and

a controller controlling the nonvolatile memory, wherein

the controller comprises first to third processors,

the first processor is a master processor and manages execution destinations of new processing that is awaiting execution and is executable by any of the first to third processors, the first processor manages the execution destinations by determining, the execution destination of the new processing managed by the first processor is the second processor if the number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and the execution destination of the new processing managed by the first processor is the third processor if the number of execution-waiting processing to be executed by the third processor is not more than a second threshold,

the controller further comprises a shared memory shared among the first to third processor, and allocates, to processing before execution, a memory area in the shared memory used for the processing before execution,

first processing is executed by any one of the second and third processors,

second processing is executed by any one of the second and third processors after execution of the first processing,

third processing is executed by any one of the second and third processors after execution of the second processing, and

the second processing receives, from the first processing, identification information indicating at least one of the first and third processing, reads information used for the second processing from a first memory area of the shared memory corresponding to the at least one of the first and third processing, and stores a result of execution of the second processing in a second memory area corresponding to the at least one of the first and third processing.

14. The memory device of claim 13, wherein the second processing reads information used for the second processing from a memory area corresponding to the first processing, and stores a result of execution of the second processing in a memory area corresponding to the third processing.