Memory device managing data in accordance with command and non-transitory computer readable recording medium
First Claim
1. A memory device comprising:
- a nonvolatile memory; and
a controller controlling the nonvolatile memory, whereinthe controller comprises first to third processors,the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and determines the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, andthe controller determines, based on priority information including priority degrees associated with the new processing, at least one of the new processing that has an execution destination determined by the first processor to be executed next by one of the second and third processors.
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Accused Products
Abstract
According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.
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Citations
14 Claims
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1. A memory device comprising:
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a nonvolatile memory; and a controller controlling the nonvolatile memory, wherein the controller comprises first to third processors, the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and determines the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, and the controller determines, based on priority information including priority degrees associated with the new processing, at least one of the new processing that has an execution destination determined by the first processor to be executed next by one of the second and third processors. - View Dependent Claims (4, 5)
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2. A memory device comprising:
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a nonvolatile memory; and a controller controlling the nonvolatile memory, wherein the controller comprises first to third processors, the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and determines the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, and the second processor determines, whether processing executed by the second processor has a dependence that next processing activated subsequent to the processing executed by the second processor is to be executed by the second processor, and, when the processing executed by the second processor has the dependence, the second processor determines that the next processing is to be executed by the second processor. - View Dependent Claims (6, 7)
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3. A memory device comprising:
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a nonvolatile memory; and a controller controlling the nonvolatile memory, wherein the controller comprises first to third processors, the first processor is a master processor and manages execution destinations of new processing that is awaiting execution, is not currently assigned to be executed by any of the first to third processors, and is executable by any of the first to third processors, the first processor manages the execution destinations by determining the execution destination of the new processing managed by the first processor is the second processor if a number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and the execution destination of the new processing managed by the first processor is the third processor if a number of execution-waiting processing to be executed by the third processor is not more than a second threshold, and the controller further comprises a shared memory shared among the first to third processor, and allocates, to processing before execution, a memory area in the shared memory used for the processing before execution. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A memory device comprising:
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a nonvolatile memory; and a controller controlling the nonvolatile memory, wherein the controller comprises first to third processors, the first processor is a master processor and manages execution destinations of new processing that is awaiting execution and is executable by any of the first to third processors, the first processor manages the execution destinations by determining, the execution destination of the new processing managed by the first processor is the second processor if the number of execution-waiting processing to be executed by the second processor is not more than a first threshold, and the execution destination of the new processing managed by the first processor is the third processor if the number of execution-waiting processing to be executed by the third processor is not more than a second threshold, the controller further comprises a shared memory shared among the first to third processor, and allocates, to processing before execution, a memory area in the shared memory used for the processing before execution, first processing is executed by any one of the second and third processors, second processing is executed by any one of the second and third processors after execution of the first processing, third processing is executed by any one of the second and third processors after execution of the second processing, and the second processing receives, from the first processing, identification information indicating at least one of the first and third processing, reads information used for the second processing from a first memory area of the shared memory corresponding to the at least one of the first and third processing, and stores a result of execution of the second processing in a second memory area corresponding to the at least one of the first and third processing. - View Dependent Claims (14)
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Specification