Arithmetic device
First Claim
1. An arithmetic device configured to receive M input signals each representing a two-state value and M coefficients corresponding respectively to the M input signals to output an output signal representing a two-state value where M is an integer larger than or equal to 2, the device comprising:
- a positive-side current source configured to output a current from a positive-side terminal, and output a first voltage corresponding to a value of 1/L of the current output from the positive-side terminal where L is an integer equal to or larger than 2;
a negative-side current source configured to output a current from a negative-side terminal, and output a second voltage corresponding to a value of 1/L of the current output from the negative-side terminal;
M cross switches that are provided corresponding to the respective M input signals;
a coefficient memory unit including M cells corresponding to the respective M coefficients; and
a comparator configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage,each of the M cells includes a first resistor and a second resistor,one end of the first resistor is connected to a first terminal of a corresponding cross switch,the other end of the first resistor is connected to a first reference potential,one end of the second resistor is connected to a second terminal of a corresponding cross switch, andthe other end of the second resistor is connected to the first reference potential.
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Accused Products
Abstract
According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.
29 Citations
12 Claims
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1. An arithmetic device configured to receive M input signals each representing a two-state value and M coefficients corresponding respectively to the M input signals to output an output signal representing a two-state value where M is an integer larger than or equal to 2, the device comprising:
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a positive-side current source configured to output a current from a positive-side terminal, and output a first voltage corresponding to a value of 1/L of the current output from the positive-side terminal where L is an integer equal to or larger than 2; a negative-side current source configured to output a current from a negative-side terminal, and output a second voltage corresponding to a value of 1/L of the current output from the negative-side terminal; M cross switches that are provided corresponding to the respective M input signals; a coefficient memory unit including M cells corresponding to the respective M coefficients; and a comparator configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage, each of the M cells includes a first resistor and a second resistor, one end of the first resistor is connected to a first terminal of a corresponding cross switch, the other end of the first resistor is connected to a first reference potential, one end of the second resistor is connected to a second terminal of a corresponding cross switch, and the other end of the second resistor is connected to the first reference potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification