Common MCU self-identification information

• US 10,176,094 B2
• Filed: 06/30/2015
• Issued: 01/08/2019
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Inventors: Brabender, Jon Matthew, Westhoff, Bernd Willi
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US14/755,101
• Publication Number:
  US 20170003910A1
• Time in Patent Office: 1,288 Days
• Field of Search: None
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.

Claims

1. A method comprising

packaging a microcontroller unit (MCU), wherein the MCU comprises a non-volatile memory, wherein the non-volatile memory is configured to store a common main program,

after the packaging, storing information in the non-volatile memory separate and apart from the stored common main program;

wherein the information comprises information specific to the MCU and a package into which the MCU is packaged, the information including at least information regarding I/O conductors of the package; and

wherein the MCU comprises a central processing unit (CPU) configured to read the information in response to executing instructions of the common main program.

2. The method of claim 1 wherein the packaging comprising an act of electrically connecting input/output (I/O) pads of the MCU to respective I/O conductors of the package, and wherein the information is transmitted to the MCU via one or more of the I/O conductors of the package.

3. The method of claim 1, wherein the common main program is stored in a range of contiguous addresses in the non-volatile memory, and wherein storing the information in the non-volatile memory comprises storing the information at a dedicated address that is separate from the range of contiguous addresses at which the common main program is stored.

4. The method of claim 1:

wherein the MCU comprises a random access memory (RAM);

wherein the information comprises a size of the RAM and a start address for the RAM;

wherein the non-volatile memory comprises a flash memory;

wherein the information comprises a size of the flash memory and a start address for the flash memory;

wherein the CPU is configured to read and process the size of the RAM, the start address for the RAM, the size of the flash memory, or the start address for the flash memory in response to executing the instructions of the common main program.

5. The method of claim 1:

wherein the MCU comprises a plurality peripherals;

wherein the information comprises a plurality of addresses for the plurality of peripherals, respectively;

wherein the information comprises a plurality of peripheral types;

wherein the information comprises a plurality of peripheral version numbers;

wherein the CPU is configured to read and process the plurality of addresses, the plurality of peripheral types, or the plurality of peripheral version numbers in response to executing the instructions of the common main program.

6. The method of claim 1:

wherein the MCU comprises a plurality of the I/O pads arranged as an MCU port;

wherein the information comprises an address for the MCU port;

wherein the information comprises an identification of the I/O pads connected to respective I/O conductors of the package.

7. The method of claim 1 wherein the information enables the common main program, once the information is stored in the non-volatile memory, to adapt itself to resources of the MCU at runtime.

8. The method of claim 1 wherein the information identifies I/O pads of the MCU that should be set to an unused state during runtime.

9. An apparatus comprising:

a microcontroller unit (MCU) contained in a package;

wherein the MCU comprises a central processing unit (CPU) and a non-volatile memory;

wherein the non-volatile memory stores information specific to the MCU and the package, the information including at least information regarding I/O conductors of the package;

wherein the non-volatile memory is configured to store a common main program separately and apart from the stored information that, when executed by the CPU, results in access of the information.

10. The apparatus of claim 9:

wherein the MCU comprises a random access memory (RAM);

wherein the information comprises a size of the RAM and a start address for the RAM;

wherein the non-volatile memory comprises a flash memory;

wherein the information comprises a size of the flash memory and a start address for the flash memory;

wherein the CPU is configured to read and process the size of the RAM, the start address for the RAM, the size of the flash memory, or the start address for the flash memory in response to executing the instructions of the common main program.

11. The apparatus of claim 10:

wherein the MCU comprises a plurality peripherals;

wherein the information comprises a plurality of addresses for the plurality of peripherals, respectively;

wherein the CPU is configured to read and process the plurality of addresses in response to executing the instructions of the common main program.

12. The apparatus of claim 10:

wherein the information comprises a plurality of peripheral types;

wherein the information comprises a plurality of peripheral version numbers;

wherein the CPU is configured to read and process the plurality of peripheral types, or the plurality of peripheral version numbers in response to executing the instructions of the common main program.

13. The apparatus of claim 10:

wherein the MCU comprises a plurality of the I/O pads arranged as an MCU port;

wherein the information comprises an address for the MCU port;

wherein the information comprises an identification of the I/O pads connected to respective I/O conductors of the package.

14. The apparatus of claim 13 wherein the information identifies I/O pads of the MCU that should be set to an unused state during runtime.

15. A method comprising:

a central processing unit (CPU) of a microcontroller unit (MCU) executing instructions of a common main program that is stored in non-volatile memory of the MCU;

the CPU reading information of a data object stored in the non-volatile memory in response to executing the instructions of the main program;

wherein the data object is separate and apart from the main program;

wherein the data object comprises information specific to the MCU and a package into which the MCU is packaged, the information including at least information regarding I/O conductors of the package.

16. The method of claim 15:

wherein the read information comprises a base address for a peripheral of the MCU;

wherein the method further comprises;

the CPU generating a control value for controlling the peripheral;

the CPU generating an address of a register in the peripheral as a function of the base address;

storing the control value in the register after generating the address.

17. The method of claim 15:

wherein the MCU comprises I/O pads;

wherein the MCU comprises drivers for selectively driving respective I/O pads to a low state, a high state, or an unused state;

wherein the package comprises I/O pins;

wherein a first plurality of the I/O pads are coupled to a plurality of the I/O pins, respectively;

wherein a second plurality of the I/O pads are not coupled to any of the I/O pins;

wherein the read information comprises information for identifying the second plurality of I/O pads;

wherein the method further comprises;

the CPU setting each of the second plurality of the I/O pads to an unused state in response to the CPU reading the information.

18. The method of claim 15:

wherein the MCU comprises a random access memory (RAM);

wherein the information comprises a size of the RAM and a start address for the RAM;

wherein the non-volatile memory comprises a flash memory;

wherein the information comprises a size of the flash memory and a start address for the flash memory;

wherein the method further comprises the CPU reading and processing the size of the RAM, the start address for the RAM, the size of the flash memory, or the start address for the flash memory in response to executing the instructions of the common main program.

19. The method of claim 15:

wherein the MCU comprises a plurality of the I/O pads arranged as an MCU port;

wherein the information comprises an address for the MCU port;

wherein the information comprises an identification of the I/O pads connected to respective I/O conductors of the package.

20. The method of claim 15 wherein the common main program is configured to be run on two MCUs having distinct resources.