Methods and systems for dynamic DRAM cache sizing

• US 10,176,107 B2
• Filed: 03/29/2014
• Issued: 01/08/2019
• Est. Priority Date: 03/29/2014
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Solihin, Yan
• Primary Examiner(s): Kim, Hong C
• Application Number:
  US15/300,272
• Publication Number:
  US 20170132144A1
• Time in Patent Office: 1,746 Days
• Field of Search: 711106, 711105, 711118, 365222, 36518525, 714754
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques described herein generally include methods and systems related to dynamic cache-sizing used to reduce the energy consumption of a DRAM cache in a chip multiprocessor. Dynamic cache sizing may be performed by adjusting the refresh interval of a DRAM cache or by combining way power-gating of the DRAM cache with adjusting the refresh interval.

Claims

1. A method of dynamic cache sizing in a volatile memory device, the method comprising:

measuring and recording a respective data storage capacity of the volatile memory device for each refresh interval of multiple refresh intervals;

receiving a target storage capacity;

selecting a refresh interval, of the multiple refresh intervals, for the volatile memory device so that the volatile memory device has a modified data storage capacity greater than or equal to the received target storage capacity, wherein each refresh interval of the multiple refresh intervals corresponds to a period of time within which rows of cells in the volatile memory device are read out and recharged; and

operating the volatile memory device at the selected refresh interval.

2. The method of claim 1, further comprising determining the modified data storage capacity for the refresh interval prior to receiving the target storage capacity.

3. The method of claim 1, wherein selecting the refresh interval for the volatile memory device comprises selecting a previously tested refresh interval based on a measured data storage capacity of the volatile memory device, wherein the data storage capacity is measured with the volatile memory device operating at the previously tested refresh interval.

4. The method of claim 1, further comprising power-gating a portion of the volatile memory device in conjunction while operating the volatile memory device at the selected refresh interval.

5. The method of claim 4, further comprising, prior to power-gating the portion of the volatile memory device:

determining a first energy saving of the volatile memory device associated with power-gating the portion of the volatile memory device in conjunction with operating the volatile memory device at the selected refresh interval;

determining a second energy saving of the volatile memory device associated with operating the volatile memory device at the selected refresh interval; and

determining that the first energy saving is greater than the second energy saving.

6. The method of claim 4, further comprising, prior to power-gating the portion of the volatile memory device, determining a size of the portion based on the received target storage capacity.

7. The method of claim 4, wherein the modified data storage capacity is a result of power-gating the portion of the volatile memory device in conjunction with operating the volatile memory device at the selected refresh interval.

8. A method of dynamic cache sizing in a volatile memory device, the method comprising:

measuring and recording a respective data storage capacity of the volatile memory device for each refresh interval of multiple refresh intervals;

receiving a target storage capacity;

determining a first energy saving of the volatile memory device associated with power-gating a portion of the volatile memory device, wherein the volatile memory device has a remainder portion with a data storage capacity that is equal to or greater than the received target storage capacity;

determining a second energy saving of the volatile memory device associated with operating the volatile memory device at a selected refresh interval of the multiple refresh intervals, wherein the data storage capacity of the volatile memory device in connection with the operation at the selected refresh interval is equal to or greater than the received target storage capacity;

comparing the first energy saving to the second energy saving; and

in response to the first energy saving being greater than the second energy saving, power-gating the portion of the volatile memory device.

9. The method of claim 8, further comprising determining the data storage capacity of the volatile memory device in connection with the operation at the selected refresh interval prior to receiving the target storage capacity.

10. The method of claim 8, further comprising in response to the second energy saving being greater than the first energy saving, operating the volatile memory device at the selected refresh interval.

11. A processor, comprising:

a processor unit;

a volatile memory device that is configured as a cache memory and is coupled to the processor unit; and

a cache memory controller coupled to the volatile memory device and configured to;

measure and record a respective data storage capacity of the volatile memory device for each refresh interval of multiple refresh intervals;

receive a target storage capacity;

select a refresh interval, of the multiple refresh intervals, for the volatile memory device so that the volatile memory device has a modified data storage capacity greater than or equal to the received target storage capacity, wherein each refresh interval of the multiple refresh intervals corresponds to a period of time within which rows of cells in the volatile memory device are read out and recharged; and

operate the volatile memory device at the selected refresh interval.

12. The processor of claim 11, wherein the modified data storage capacity is determined for the refresh interval prior to the receipt of the target storage capacity by the cache memory controller.

13. The processor of claim 11, wherein the cache memory controller is configured to select the refresh interval for the volatile memory device by selection of a previously tested refresh interval based on a measured data storage capacity of the volatile memory device, wherein the measured data storage capacity is measured with the volatile memory device operative at the previously tested refresh interval.

14. The processor of claim 11, wherein the cache memory controller is further configured to power-gate a portion of the volatile memory device in conjunction with the operation of the volatile memory device at the selected refresh interval.

15. The processor of claim 14, wherein the cache memory controller is further configured to:

prior to the power-gate of the portion of the volatile memory device;

determine a first energy saving of the volatile memory device associated with the power-gate of the portion of the volatile memory device in conjunction with the operation of the volatile memory device at the selected refresh interval;

determine a second energy saving of the volatile memory device associated with the operation of the volatile memory device at the selected refresh interval; and

determine that the first energy saving is greater than the second energy saving.

16. The processor of claim 14, wherein the cache memory controller is further configured to, prior to the power-gate of the portion of the volatile memory device, determine a size of the portion based on the received target storage capacity.

17. The processor of claim 14, wherein the modified data storage capacity is a result of the power-gate of the portion of the volatile memory device in conjunction with the operation of the volatile memory device at the selected refresh interval.

18. A processor, comprising:

a processor unit;

a volatile memory device that is configured as a cache memory and is coupled to the processor unit; and

a cache memory controller coupled to the volatile memory device and configured to;

measure and record a respective data storage capacity of the volatile memory device for each refresh interval of multiple refresh intervals;

receive a target storage capacity;

determine a first energy saving of the volatile memory device associated with power-gate of a portion of the volatile memory device, wherein the volatile memory device has a remainder portion with a data storage capacity that is equal to or greater than the received target storage capacity;

determine a second energy saving of the volatile memory device associated with operation of the volatile memory device at a selected refresh interval, wherein the data storage capacity of the volatile memory device in connection with the operation at the selected refresh interval is equal to or greater than the received target storage capacity;

compare the first energy saving to the second energy saving; and

in response to the first energy saving being greater than the second energy saving, power-gate the portion of the volatile memory device.

19. The processor of claim 18, wherein the data storage capacity of the volatile memory device in connection with the operation at the selected refresh interval is measured prior to the receipt of the target storage capacity by the cache memory controller.