Row identification number generation in database direct memory access engine

• US 10,176,114 B2
• Filed: 11/28/2016
• Issued: 01/08/2019
• Est. Priority Date: 11/28/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Brown, David A., Idicula, Sam, Schlanger, Erik, Jain, Rishabh, Duller, Michael
• Primary Examiner(s): Tseng, Cheng Yuan
• Application Number:
  US15/362,693
• Publication Number:
  US 20180150407A1
• Time in Patent Office: 771 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/656 Address space sharing

Abstract

Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine. Tabular data is efficiently copied between internal memories of the data movement system via a copy ring that is coupled to the internal memories of the data movement system and/or is coupled to a data movement engine. Also, a data movement engine internally broadcasts data to other data movement engines, which then transfer the data to respective core processors. Partitioning may also be performed by the hardware of the data movement system. Techniques are used to partition data “in flight”. The data movement system also generates a column of row identifiers (RIDs). A row identifier is a number treated as identifying a row or element'"'"'s position within a column. Row identifiers each identifying a row in column are also generated.

Claims

1. A method for generating row identifiers (RIDs) for one or more columns:

storing a first descriptor at a particular memory location, said first descriptor indicating;

an attribute specifying to generate a RID column comprising a particular sequence of RIDs;

a destination memory location for said RID column;

in response to said particular memory location being pushed into a first register within a register space that is accessible by a first set of electronic circuits;

said first set of electronic circuits accessing said first descriptor stored at said particular memory location;

said first set of electronic circuits generating an ordered sequence of RIDs;

said first set of electronic circuits storing said RID column at said destination memory location, said particular sequence of RIDs in said RID column including at least a portion of said ordered sequence of RIDs.

2. The method of claim 1, wherein said first descriptor specifies a counter value specifying a difference between successive RIDs in said ordered sequence of RIDs.

3. The method of claim 1, wherein said first descriptor specifies a column width for said RID column.

4. The method of claim 1, wherein generating said ordered sequence of RIDs includes generating said ordered sequence of RIDs beginning with a starting value.

5. The method of claim 4, further including:

storing a second descriptor at another memory location, said second descriptor indicating said starting value; and

in response to said another memory location being pushed into said first register within a first register space that is accessible by said first set of electronic circuits;

configuring said first set of electronic circuits to generate said ordered sequence of RIDs beginning with said starting value.

6. The method of claim 5, wherein configuring said first set of electronic circuits includes setting a particular register to a value based on said starting value, said particular register being identified by said second descriptor.

7. The method of claim 4, wherein said first descriptor specifies said starting value.

8. The method of claim 1, wherein said first descriptor specifies a tabular data manipulation operation, wherein the method further includes applying said tabular data manipulation operation to said ordered sequence of RIDs to generate said RID column stored at said destination memory location.

9. The method of claim 8, wherein said tabular data manipulation operation is a gather operation based on a bit vector.

10. The method of claim 8, further including performing row resolution using said RID column stored at said destination memory location on a second column.

11. The method of claim 8, further including:

storing a second descriptor at another memory location, wherein said second descriptor specifies;

a source memory location for a second column;

a second destination memory location;

said data manipulation operation;

in response to said another memory location being pushed into said first register within a first register space that is accessible by said first set of electronic circuits, said first set of electronic circuits;

applying data manipulation operation to a column stored at second source memory location; and

storing a resultant column resulting from said applying said data manipulation operation at said second destination memory location.

12. A method, comprising:

storing a first descriptor at a first descriptor memory location, said first descriptor indicating;

an attribute specifying to generate a RID column comprising an ordered sequence of RIDs;

a first destination memory location for said RID column;

in response to the first descriptor memory location being pushed into a register within a register space that is accessible by a first set of electronic circuits, said first set of electronic circuits generating and storing said RID column at said first destination memory location;

storing each core partitioning descriptor of a set of core partitioning descriptors in a respective descriptor memory location;

wherein each core partitioning descriptor of said set of core partitioning descriptors specifies a respective source memory location of a respective column wherein the respective source memory location specified by a certain core partitioning descriptor of said set of core partition descriptors is the first destination memory location of said RID column;

in response to each respective descriptor memory location of the set of core partitioning descriptors being pushed into a register within a register space that is accessible by a first set of electronic circuits;

for each core partitioning descriptor of said set of core partitioning descriptors, partitioning the respective column of said core partitioning descriptor between scratch pad memories of core processors that are each coupled to said first set of electronic circuits.

13. The method of claim 12, wherein for said certain core partitioning descriptor of said set of core partitioning descriptors, partitioning the respective column includes storing a resultant RID column in a particular core processor of said core processors, said resultant RID column comprising a portion of said ordered sequence of RIDs, wherein the method further includes performing row resolution against another column based on said resultant RID column.

14. The method of claim 12, wherein said first descriptor specifies a counter value specifying a difference between successive RIDs in said ordered sequence of RIDs.

15. The method of claim 12, wherein said first descriptor specifies a column width for said RID column.

16. The method of claim 12, wherein generating and storing said RID column includes generating said ordered sequence of RIDs beginning with a starting value specified in a descriptor.

17. A chip comprising electronic circuitry being configured for generating row identifiers (RIDs) for one or more columns, said electronic circuitry being configured for:

storing a first descriptor at a particular memory location, said first descriptor indicating;

an attribute specifying to generate a RID column comprising a particular sequence of RIDs;

a destination memory location for said RID column;

in response to said particular memory location being pushed into a first register within a register space that is accessible by a first set of electronic circuits;

said first set of electronic circuits accessing said first descriptor stored at said particular memory location;

said first set of electronic circuits generating an ordered sequence of RIDs;

said first set of electronic circuits storing said RID column at said destination memory location, said particular sequence of RIDs in said RID column including a least a portion of said ordered sequence of RIDs.

18. The chip of claim 17, wherein said first descriptor specifies a counter value specifying a difference between successive RIDs in said ordered sequence of RIDs.

19. A chip comprising electronic circuitry configured for:

storing a first descriptor at a first descriptor memory location, said first descriptor indicating;

an attribute specifying to generate a RID column comprising an ordered sequence of RIDs;

a first destination memory location for said RID column;

in response to the first descriptor memory location being pushed into a register within a register space that is accessible by a first set of electronic circuits, said first set of electronic circuits generating and storing said RID column at said first destination memory location;

storing each core partitioning descriptor of a set of core partitioning descriptors in a respective descriptor memory location;

wherein each core partitioning descriptor of said set of core partitioning descriptors specifies a respective source memory location of a respective column

wherein the respective source memory location specified by a certain core partitioning descriptor of said set of core partition descriptors is the first destination memory location of said RID column;

in response to each respective descriptor memory location of the set of core partitioning descriptors being pushed into a register within a register space that is accessible by a first set of electronic circuits;

for each core partitioning descriptor of said set of core partitioning descriptors, partitioning the respective column of said core partitioning descriptor between scratch pad memories of core processors that are each coupled to said first set of electronic circuits.

20. The chip of claim 19, wherein for said certain core partitioning descriptor of said set of core partitioning descriptors, partitioning the respective column includes storing a resultant RID column in a particular core processor of said core processors, said resultant RID column comprising a portion of said ordered sequence of RIDs, wherein the electronic circuitry is further configured for performing row resolution against another column based on said resultant RID column.