Analog neuromorphic circuits for dot-product operation implementing resistive memories

• US 10,176,425 B2
• Filed: 07/14/2017
• Issued: 01/08/2019
• Est. Priority Date: 07/14/2016
• Status: Active Grant

• Current Assignee: University of Dayton
• Original Assignee: University of Dayton
• Inventors: Yakopcic, Chris, Taha, Tarek M., Hasan, Md Raqibul
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/650,145
• Publication Number:
  US 20180018559A1
• Time in Patent Office: 543 Days
• Field of Search: 365 46, 365 94, 365100, 365129, 365148, 365158, 365163, 257 2- 5, 257 9, 257295, 257310, 257E2135, 438 95, 438 96, 438135, 438166, 438240, 438365, 438482, 438486, 438597, 438785
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods

Abstract

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Claims

1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:

a plurality of input voltages applied to the analog neuromorphic circuit, wherein each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with a plurality of matrix values included in a matrix;

a plurality of resistive memories with each resistive memory configured to provide a resistance value to each corresponding input voltage, wherein each resistance value is a positive resistance value selected from a finite range of resistance values; and

a controller configured to;

pair each resistive memory with another resistive memory from the plurality of resistive memories so that each pair of resistive memories includes a pair of resistance values,

convert each pair of resistance values from a pair of positive resistance values selected from the finite range of resistance values to a single non-binary value, wherein each single non-binary value is mapped to a matrix value included in the matrix that is incorporated into the dot-product operation with the vector values included in the vector, and

generate a plurality of dot-product operation values from the dot-product operation with the vector and the matrix, wherein each dot-product operation value is a non-binary value.

2. The analog neuromorphic circuit of claim 1, wherein the controller is further configured to:

map each positive matrix value into a first relationship with the corresponding pair of resistive memories so that the first relationship converts the corresponding pair of positive resistance values selected from the finite range of resistance values to a positive single non-binary value that represents the positive matrix value; and

map each negative matrix value into a second relationship with the corresponding pair of resistive memories so that the second relationship converts the corresponding pair of positive resistance values selected from the finite range of resistance values to a negative single non-binary value that represents the negative matrix value.

3. The analog neuromorphic circuit of claim 2, wherein the controller is further configured to:

each positive matrix value into a co-linear first relationship with the corresponding pair of resistive memories so that the co-linear first relationship converts a corresponding pair of conductance values selected from a finite range of conductance values to the positive single non-binary value that represents the positive matrix value; and

map each negative matrix value into a co-linear second relationship with the corresponding pair of resistive memories so that the co-linear second relationship converts a corresponding pair of conductance values selected from the finite range of conductance values to the negative single non-binary value that represents the negative matrix value.

4. The analog neuromorphic circuit of claim 1, wherein each input voltage applied to the analog neuromorphic circuit is propagated through the plurality of resistive memories so that each resistance value of each resistive memory contributes to a generation of a plurality of output voltage signals.

5. The analog neuromorphic circuit of claim 4, wherein each output voltage signal is generated from the dot-product operation of the vector and the matrix so that each output voltage signal is representative of each corresponding dot-product operation value.

6. The analog neuromorphic circuit of claim 5, further comprising:

a plurality of comparators with each comparator configured to convert each output voltage signal that is representative of each corresponding dot-product operation value from a voltage value to a non-binary value that is representative of the dot-product operation of the vector and the matrix.

7. The analog neuromorphic circuit of claim 1, wherein each resistive memory is a memristor.