Integrated gate driver

• US 10,176,752 B2
• Filed: 03/24/2015
• Issued: 01/08/2019
• Est. Priority Date: 03/24/2014
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Azizi, Yaser
• Primary Examiner(s): Sim, Matthew
• Application Number:
  US14/666,372
• Publication Number:
  US 20150269883A1
• Time in Patent Office: 1,386 Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A gate driver suitable for integration with the backplane of an AMOLED display includes first and second clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of the clock signals is active the other of the clock signals is inactive, and active portions of the first and second clock signals do not overlap. In a daisy chain of circuits for producing gate signals, each of the circuits except the last has an output coupled to the input of the next circuit in the chain. A source of a start token signal is coupled to an input of a first circuit in the daisy chain. Each of the circuits is configured to produce a gate signal one clock cycle after an active portion of one of the clock signals is received.

Claims

1. A gate driver suitable for integration with the backplane of an active matrix organic light emitting diode (AMOLED) display, said gate driver comprising

clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of said clock signals is active the other of said clock signals is inactive, and active portions of said first and second clock signals do not overlap;

a daisy chain of more than two circuits integrated within said backplane and for producing gate signals, each of said circuits including capacitors and thin film transistors and substantially physically identical to one another and receiving as inputs both said first and second clock signals, each of said circuits receiving over first one or more clock inputs one of said first and second clock signals and receiving over second one or more clock inputs the other of said first and second clock signals, the first one or more clock inputs of each circuit receiving the same clock signal as the second one or more clock inputs of adjacent circuits, and the second one or more clock inputs of each circuit receiving the same clock signal as the first one or more clock inputs of adjacent circuits, each of said circuits except the first circuit in the daisy chain receiving as the only input from said circuits, one or more gate signal outputs, all from only one adjacent circuit of said circuits, and each of said circuits except the last circuit in the daisy chain having an output coupled to an input of an adjacent circuit in the daisy chain; and

a source of a start token signal coupled to an input of the first circuit in said daisy chain;

wherein each of said circuits is configured to produce a gate signal one clock cycle after an active portion of one of said clock signals is received.

2. The gate driver of claim 1 which is configured for use with an AMOLED display comprising p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage.

3. The gate driver of claim 1 in which said gate signals are active low for selecting or addressing p-type thin film transistors.

4. The gate driver of claim 1 in which said gate signals are active high for selecting or addressing n-type thin film transistors.

5. The gate driver of claim 1 in which said circuits produce consecutive gate signals with a predetermined time gap between each pair of consecutive gate signals.

6. The gate driver of claim 5 in which said active portions of said first and second clock signals have a predetermined time gap between them, to produce said time gap between each pair of consecutive gate signals.

7. An integrated gate driver for performing emission operations of a display, the gate driver comprising:

a source of first and second clock signals each, having alternating active and inactive portions configured such that when one is active the other is inactive and active signals do not overlap;

a source for a start token signal and an inverse start token signal for input into a first circuit block;

integrated within a backplane of the display alternating odd and even circuit blocks of more than two circuit blocks daisy chained together such that an output of one circuit block is connected to an input of the next circuit block and each circuit block receives as inputs both first and second clock signals, each odd and even circuit block including capacitors and thin film transistors and substantially physically identical to one another, each of said circuit blocks receiving over first one or more clock inputs one of said first and second clock signals and receiving over second one or more clock inputs the other of said first and second clock signal, the first one or more clock inputs of each odd circuit block receiving the same clock signal as the second one or more clock inputs of each even circuit block, and the second one or more clock inputs of each odd circuit block receiving the same clock signal as the first one or more clock inputs of each even circuit block, each of said circuit blocks except the first circuit block in the chain receiving as the only input from said circuit blocks, one or more gate signal outputs, all from only one adjacent circuit block of said circuit blocks, wherein each circuit block is configured to produce an active output one clock cycle after an active signal is received and an inactive output at all other times.

8. The integrated gate driver of claim 7 configured for use with a display comprising p-type transistors so that an active signal corresponds with a high voltage and an inactive signal corresponds with a low voltage.

9. The integrated gate driver of claim 7 wherein the alternating circuit blocks are configured to select a line of pixels for two clock cycles in order to allow time for the pixels to settle before being programmed.

10. A method of producing gate signals from a gate driver integrated with the backplane of an active matrix organic light emitting diode (AMOLED) display, said method comprising

producing first and second clock signals each having alternating active and inactive portions configured such that when one of said clock signals is active the other of said clock signals is inactive, and active portions of said first and second clock signals do not overlap;

producing gate signals from a daisy chain of more than two circuits integrated within said backplane, each of said circuits including capacitors and thin film transistors and substantially physically identical to one another and receiving as inputs both said first and second clock signals, each of said circuits receiving over first one or more clock inputs one of said first and second clock signals and receiving over second one or more clock inputs the other of said first and second clock signals, the first one or more clock inputs of each circuit receiving the same clock signal as the second one or more clock inputs of adjacent circuits, and the second one or more clock inputs of each circuit receiving the same clock signal as the first one or more clock inputs of adjacent circuits, each of said circuits except the first circuit in the daisy chain receiving as the only input from said circuits, one or more gate signal outputs, all from only one adjacent circuit of said circuits, and each of said circuits except the last circuit in the daisy chain having an output coupled to an input of an adjacent circuit in the daisy chain;

supplying a start token signal to an input of a first circuit in said daisy chain; and

producing a gate signal from each of said circuits, each gate signal being produced one clock cycle after said start token signal or an active portion of one of said clock signals is received.

11. The method of claim 10 in which the AMOLED display comprises p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage.

12. The method of claim 10 in which said gate signals are active low for selecting or addressing p-type thin film transistors.

13. The method of claim 10 in which said gate signals are active high for selecting or addressing n-type thin film transistors.

14. The method of claim 10 which produces consecutive gate signals with a predetermined time gap between each pair of consecutive gate signals.

15. The method of claim 14 in which said active portions of said first and second clock signals have a predetermined time gap between them, to produce said time gap between each pair of consecutive gate signals.