Adjusting instruction delays to the latch path in DDR5 DRAM

• US 10,176,858 B1
• Filed: 08/30/2017
• Issued: 01/08/2019
• Est. Priority Date: 08/30/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wilmoth, David D., Brown, Jason M.
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Dinh, Minh
• Application Number:
  US15/691,394
• Time in Patent Office: 496 Days
• Field of Search: 36523008
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

Claims

1. A memory device comprising:

a command interface comprising;

clock input circuitry configured to provide a clock signal;

gating circuitry configured to generate a gated clock signal based on the clock signal and on a received chip select (CS) signal;

chip select (CS) input circuitry configured to receive the CS signal, wherein the CS input circuitry comprises a delay element disposed between an input buffer and a CS latch configured to provide the CS signal; and

command/address (CA) input circuitry comprising a CA latch, wherein the CA input circuitry is configured to receive the gated clock signal and provide a latched command/address signal; and

wherein the command interface is configured to operate in a CS training mode wherein the memory device is configured to provide a CS training signal in response to the received CS signal, and wherein the CS signal is advanced based on the delay of the delay element.

2. The memory device of claim 1, wherein the gating circuitry comprises an AND gate configured to receive the clock signal and the CS signal and provide the gated clock signal.

3. The memory device of claim 1, wherein the gating circuitry comprises:

a first half-latch configured to receive the CS signal and provide a latency to a CS signal; and

a second half-latch configured to receive the CS signal from the first half-latch.

4. The memory device of claim 3, wherein the first and the second half-latches comprise a first latency for the CS signal, and wherein the clock input circuitry comprises a clock delay element configured to match the first latency.

5. The memory device of claim 1, wherein the command interface comprises a transmission line configured to carry the gated clock signal from the gating circuitry to the CA input circuitry, the transmission line comprising at least one buffer.

6. The memory device of claim 1, wherein the gated signal received by the CA input circuitry comprises a second latency, and wherein the CA input circuitry comprises a CA delay element configured to match the second latency.

7. The memory device of claim 1, wherein the memory device comprises a training mode for the CS signal.

8. The memory device of claim 1, wherein the memory device comprises an access time (tAA) in a range between 14 and 18 ps.

9. A semiconductor device comprising:

a command interface configured to receive a clock signal, a chip select (CS) signal, and a command/address (CA) signal, the command interface circuitry comprising CS delay circuitry configured to delay the received CS signal, wherein the command interface is configured to operate in a CS training mode wherein the semiconductor device is configured to provide a CS training signal in response to the received CS signal, and wherein the CS signal is advanced based on the delay of the CS delay circuitry;

memory circuitry configured to store data; and

an input/output (I/O) interface configured to provide the stored data based on the CS signal and the CA signal;

wherein the semiconductor device comprises an access time (tAA) that comprises a time interval between receiving the CA signal and providing the stored data, and wherein a delay of the CS delay circuitry enables a reduction in the tAA.

10. The semiconductor device of claim 9, wherein the command interface comprises gating circuitry configured to gate the received CA signal based on the received CS signal.

11. The semiconductor device of claim 10, wherein the gating circuitry comprises a first latency, and wherein the delay of the CS delay circuitry is determined based on the first latency.

12. The semiconductor device of claim 11, wherein the delay of the CS delay circuitry is equal to the first latency.

13. The semiconductor device of claim 10, wherein the gating circuitry comprises logic circuitry configured to receive a clock signal and the received CS signal and to provide a gated clock signal configured to gate the received the CA signal.

14. The semiconductor device of claim 13, wherein the command interface comprises clock delay circuitry.

15. The semiconductor device of claim 9, wherein the command interface comprises an input buffer configured to receive the CS signal and to provide the CS signal to the CS delay circuitry, and a CS latch configured to receive a delayed CS signal.

16. A method to operate a memory device, the method comprising:

in a training mode;

receiving a chip select (CS) signal;

delaying the CS signal using delay circuitry; and

providing a training signal based on the delayed CS signal; and

in a non-training mode;

receiving the CS signal;

latching a command/address (CA) signal based on the received CS signal;

delaying the CS signal using the delay circuitry; and

latching the delayed received CS signal;

wherein a clock skew between the latched CA signal and the latched CS signal is significantly smaller than a clock cycle of the memory device.

17. The method of claim 16, wherein latching the CA signal comprises:

receiving a clock signal;

gating the clock signal using the received CS signal; and

providing the gated lock signal to a CA latch that latches the CA signal.

18. The method of claim 16, wherein delaying the CS signal in the training mode is configured to cause user circuitry that provides the CS signal and receives the training signal to advance the CS signal.

19. The method of claim 18, wherein the user circuitry comprises a processor.