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Package-on-package semiconductor assembly having bottom device confined by dielectric recess

  • US 10,177,090 B2
  • Filed: 02/03/2016
  • Issued: 01/08/2019
  • Est. Priority Date: 07/28/2015
  • Status: Active Grant
First Claim
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1. A package-on-package semiconductor assembly, comprising:

  • a core base that includes a dielectric layer, a resin sealant layer and an array of metal posts, wherein (i) the dielectric layer has a recess extending from a top surface of the dielectric layer, (ii) the resin sealant layer is disposed over the top surface of the dielectric layer, and (iii) the metal posts are disposed in the resin sealant layer;

    a first semiconductor device that includes a semiconductor chip, a re-distribution layer and a mold compound, the re-distribution layer having active pads at a bottom surface thereof and the semiconductor chip being disposed over a top surface of the re-distribution layer and electrically coupled to the active pads of the re-distribution layer and surrounded by the mold compound, wherein the first semiconductor device is laterally confined within the recess of the dielectric layer and with the active pads of the re-distribution layer attached to a floor of the recess of the dielectric layer by an adhesive;

    a bottom buildup circuitry under a bottom surface of the core base, wherein the bottom buildup circuitry is electrically coupled to the active pads of the re-distribution layer of the first semiconductor device through metallized vias that extend through the adhesive and the dielectric layer and is further electrically coupled to the metal posts through additional metallized vias that extend through the dielectric layer; and

    a second semiconductor device over a top surface of the core base, wherein the second semiconductor device is electrically coupled to the first semiconductor device through the metal posts and the bottom buildup circuitry.

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