Package-on-package semiconductor assembly having bottom device confined by dielectric recess

• US 10,177,090 B2
• Filed: 02/03/2016
• Issued: 01/08/2019
• Est. Priority Date: 07/28/2015
• Status: Active Grant

• Current Assignee: Bridge Semiconductor Corporation
• Original Assignee: Bridge Semiconductor Corporation
• Inventors: Lin, Charles W. C., Wang, Chia-Chung
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US15/015,050
• Publication Number:
  US 20170033083A1
• Time in Patent Office: 1,070 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/117 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 being a land array, e.g. LGA

Abstract

A package-on-package semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between two both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, another semiconductor device is disposed over a top surface of the core base and is electrically coupled to the semiconductor device in the dielectric recess through a buildup circuitry under a bottom surface of the core base.

Claims

1. A package-on-package semiconductor assembly, comprising:

a core base that includes a dielectric layer, a resin sealant layer and an array of metal posts, wherein (i) the dielectric layer has a recess extending from a top surface of the dielectric layer, (ii) the resin sealant layer is disposed over the top surface of the dielectric layer, and (iii) the metal posts are disposed in the resin sealant layer;

a first semiconductor device that includes a semiconductor chip, a re-distribution layer and a mold compound, the re-distribution layer having active pads at a bottom surface thereof and the semiconductor chip being disposed over a top surface of the re-distribution layer and electrically coupled to the active pads of the re-distribution layer and surrounded by the mold compound, wherein the first semiconductor device is laterally confined within the recess of the dielectric layer and with the active pads of the re-distribution layer attached to a floor of the recess of the dielectric layer by an adhesive;

a bottom buildup circuitry under a bottom surface of the core base, wherein the bottom buildup circuitry is electrically coupled to the active pads of the re-distribution layer of the first semiconductor device through metallized vias that extend through the adhesive and the dielectric layer and is further electrically coupled to the metal posts through additional metallized vias that extend through the dielectric layer; and

a second semiconductor device over a top surface of the core base, wherein the second semiconductor device is electrically coupled to the first semiconductor device through the metal posts and the bottom buildup circuitry.

2. The package-on-package semiconductor assembly of claim 1, wherein the dielectric layer contains glass fiber whereas the resin sealant layer is free of glass fiber.

3. The package-on-package semiconductor assembly of claim 1, further comprising a top buildup circuitry over the top surface of the core base and between the core base and the second semiconductor device, wherein the second semiconductor device is electrically coupled to the top buildup circuitry, and the top buildup circuitry is electrically coupled to the first semiconductor device through the metal posts and the bottom buildup circuitry.

4. The package-on-package semiconductor assembly of claim 1, wherein the core base further includes an array of auxiliary metal pads laterally covered by the dielectric layer and electrically coupled to and disposed between the metal posts and the additional metallized vias of the bottom buildup circuitry.

5. The package-on-package semiconductor assembly of claim 4, wherein the auxiliary metal pads have a thickness substantially equal to a depth of the recess of the dielectric layer.

6. A package-on-package semiconductor assembly, comprising:

a core base that includes a dielectric layer, a resin sealant layer, and an array of metal posts, wherein (i) the dielectric layer has a recess extending from a top surface of the dielectric layer and an array of through-holes extending through the dielectric layer at a floor of the recess, (ii) the resin sealant layer is disposed over the top surface of the dielectric layer, and (iii) the metal posts are disposed in the resin sealant layer;

a first semiconductor device that includes a semiconductor chip, a re-distribution layer and a mold compound, the re-distribution layer having active pads at a bottom surface thereof and the semiconductor chip being disposed over a top surface of the re-distribution layer and electrically coupled to the active pads of the re-distribution layer and surrounded by the mold compound, wherein the first semiconductor device is laterally confined within the recess of the dielectric layer and with the active pads of the re-distribution layer attached to the floor of the recess of the dielectric layer by an adhesive, wherein the first semiconductor device has protruded bumps that extend from selected ones of the active pads of the re-distribution layer through the through-holes at the floor;

a bottom buildup circuitry under a bottom surface of the core base, wherein the bottom buildup circuitry is electrically coupled to the protruded bumps of the first semiconductor device and is further electrically coupled to the metal posts through metallized vias that extend through the dielectric layer; and

a second semiconductor device over a top surface of the core base, wherein the second semiconductor device is electrically coupled to the first semiconductor device through the metal posts and the bottom buildup circuitry.

7. The package-on-package semiconductor assembly of claim 6, further comprising a top buildup circuitry over the top surface of the core base and between the core base and the second semiconductor device, wherein the second semiconductor device is electrically coupled to the top buildup circuitry, and the top buildup circuitry is electrically coupled to the first semiconductor device through the metal posts and the bottom buildup circuitry.