Semiconductor package structure, package on package structure and packaging method
First Claim
1. A semiconductor package structure, comprising:
- a substrate having a lateral surface, a first surface and a second surface opposite to the first surface and a first coefficient of thermal expansion CTE1;
a first semiconductor device disposed adjacent to the first surface of the substrate, wherein the first semiconductor device is a semiconductor die;
a first encapsulant having a side surface, the first encapsulant disposed on the first surface of the substrate, covering at least a portion of the first semiconductor device, and having a second coefficient of thermal expansion CTE2; and
a second encapsulant having a side surface, the second encapsulant disposed on the second surface of the substrate and having a third coefficient of thermal expansion CTE3,wherein a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3, and the side surface of the first encapsulant, the side surface of the second encapsulant and the lateral surface of the substrate are substantially coplanar.
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Accused Products
Abstract
A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first coefficient of thermal expansion CTE1. The first semiconductor device is disposed adjacent to a first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate, and covers at least a portion of the first semiconductor device. The first encapsulant has a second coefficient of thermal expansion CTE2. The second encapsulant is disposed on a second surface of the substrate and has a third coefficient of thermal expansion CTE3. A difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3.
12 Citations
21 Claims
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1. A semiconductor package structure, comprising:
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a substrate having a lateral surface, a first surface and a second surface opposite to the first surface and a first coefficient of thermal expansion CTE1; a first semiconductor device disposed adjacent to the first surface of the substrate, wherein the first semiconductor device is a semiconductor die; a first encapsulant having a side surface, the first encapsulant disposed on the first surface of the substrate, covering at least a portion of the first semiconductor device, and having a second coefficient of thermal expansion CTE2; and a second encapsulant having a side surface, the second encapsulant disposed on the second surface of the substrate and having a third coefficient of thermal expansion CTE3, wherein a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3, and the side surface of the first encapsulant, the side surface of the second encapsulant and the lateral surface of the substrate are substantially coplanar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 20, 21)
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12. A package on package structure, comprising:
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a bottom package, comprising; a bottom substrate having a first surface and a second surface opposite to the first surface and having a first coefficient of thermal expansion CTE1; a first semiconductor device disposed adjacent to the first surface of the bottom substrate; a first encapsulant disposed on the first surface of the bottom substrate, covering at least a portion of the first semiconductor device, and having a second coefficient of thermal expansion CTE2; and a second encapsulant disposed on the second surface of the bottom substrate and having a third coefficient of thermal expansion CTE3, wherein a difference between CTE1 and CTE2 is substantially equal to a difference between CTE1 and CTE3; and a top package disposed on and electrically connected to the bottom package, and comprising; a top substrate having a first surface and a second surface opposite to the first surface, and having a fourth coefficient of thermal expansion CTE4; a top semiconductor device disposed adjacent to the first surface of the top substrate; and a top encapsulant disposed on the first surface of the top substrate, covering at least a portion of the top semiconductor device, and having a fifth coefficient of thermal expansion CTE5, wherein CTE5 is substantially equal to CTE4. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification