Semiconductor device and structure

• US 10,177,147 B2
• Filed: 04/21/2016
• Issued: 01/08/2019
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Yiwei
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US15/134,897
• Publication Number:
  US 20160336316A1
• Time in Patent Office: 992 Days
• CPC Class Codes: H01L 2027/11837 Implementation of digital circuits
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate, comprising;

first, second, third, fourth PMOS transistors, wherein the first, second, third and fourth PMOS transistors are disposed in a first row; and

first, second, third, fourth NMOS transistors, wherein the first, second, third and fourth NMOS transistors are disposed in a second row adjacent to the first row;

a plurality of metal layers on the semiconductor substrate; and

an oxide diffusion (OD) layer in the semiconductor substrate,

wherein gates of the first PMOS and NMOS transistors are connected together for receiving an input signal through the metal layers,

wherein gates of the second PMOS and NMOS transistors are connected together through the metal layers,

wherein gates of the third PMOS and NMOS transistors are connected together through the metal layers, wherein gates of the fourth PMOS and NMOS transistors are connected together through the metal layers, and drains of the fourth PMOS and NMOS transistors are connected together for providing an output signal via the metal layer,

wherein the first, second, third and fourth NMOS transistors are connected in parallel through the metal layers and the OD layer, the first, second, third and fourth PMOS transistors are connected in parallel through the metal layers and the OD layer, or

wherein the first and second NMOS transistors are connected in serial through the metal layers and the OD layer, and the first and second PMOS transistors are connected in serial through the metal layers and the OD layer, or

wherein the third and fourth NMOS transistors are connected in serial through the metal layers and the OD layer, and the third and fourth PMOS transistors are connected in serial through the metal layers and the OD layer.

2. The semiconductor structure as claimed in claim 1, wherein the first NMOS and PMOS transistors are disposed in a first column, the second NMOS and PMOS transistors are disposed in a second column adjacent to the first column, the third NMOS and PMOS transistors are disposed in a third column adjacent to the second column, and the fourth NMOS and PMOS transistors are disposed in a fourth column adjacent to the third column.

3. The semiconductor structure as claimed in claim 2, wherein the second column is arranged between the first and third columns, and the third column is arranged between the second and fourth columns.

4. The semiconductor structure as claimed in claim 1, wherein the gates of the first, second, third and fourth NMOS transistors and the gates of the first, second, third and fourth PMOS transistors are connected together for receiving the input signal.

5. The semiconductor structure as claimed in claim 4, wherein the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, and the output signal is complementary to the input signal with a first delay time.

6. The semiconductor structure as claimed in claim 1, wherein the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, and the gates of the first, second, third and fourth NMOS transistors and the gates of the first, second, third and fourth PMOS transistors are connected together for receiving the input signal, and the output signal is complementary to the input signal.

7. The semiconductor structure as claimed in claim 1, wherein the first, second, third and fourth NMOS transistors are the same size, and the first, second, third and fourth PMOS transistors are the same size.

8. The semiconductor structure as claimed in claim 1, wherein the first, second, third and fourth NMOS transistors are connected in parallel, and sources of the first, second, third and fourth NMOS transistors are coupled to a ground, and the first, second, third and fourth PMOS transistors are connected in parallel, and sources of the first, second, third and fourth PMOS transistors are coupled to a supply voltage.