Systems and methods for high precision and/or low loss regulation of output currents of power conversion systems

• US 10,177,665 B2
• Filed: 02/09/2017
• Issued: 01/08/2019
• Est. Priority Date: 07/19/2013
• Status: Active Grant

• Current Assignee: On-Bright Electronics (Shanghai) Co., Ltd. (Orthosie Investment Holdings Ltd.)
• Original Assignee: On-Bright Electronics (Shanghai) Co., Ltd. (Orthosie Investment Holdings Ltd.)
• Inventors: Zhu, Liqiang, Yang, Jiqing, Chen, Yaozhang, Li, Zhuoyan, Luo, Qiang, Fang, Lieyi
• Primary Examiner(s): Tran, Nguyen
• Application Number:
  US15/428,996
• Publication Number:
  US 20170214327A1
• Time in Patent Office: 698 Days
• Field of Search: 363 20, 363 2104, 363 2105, 363 2107, 363 2108, 363 2109, 363 211, 363 2111, 363 2112, 363 3, 363 2115- 2118
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H05B 45/325 Pulse-width modulation [PWM]
• CPC Class Codes: H05B 45/38 using boost topology
• CPC Class Codes: H05B 45/382 with galvanic isolation between input and output

Abstract

Systems and methods are provided for signal processing. An example error amplifier for processing a reference signal and an input signal associated with a current of a power conversion system includes a first operational amplifier, a second operational amplifier, a first transistor, a second transistor, a current mirror component, a switch, a first resistor and a second resistor. The first operational amplifier includes a first input terminal, a second input terminal and a first output terminal, the first input terminal being configured to receive a reference signal. The first transistor includes a first transistor terminal, a second transistor terminal and a third transistor terminal, the first transistor terminal being configured to receive a first amplified signal from the first output terminal, the third transistor terminal being coupled to the second input terminal.

Claims

1. An error amplifier for a reference signal and an input signal associated with a current of a power converter, the error amplifier comprising:

a first operational amplifier including a first input terminal, a second input terminal and a first output terminal, the first input terminal being configured to receive a reference signal, the first output terminal configured to output a first amplified signal to a first transistor terminal of a first transistor, the first transistor further including a second transistor terminal and a third transistor terminal, and the second input terminal being coupled to the third transistor terminal;

a second operational amplifier including a third input terminal, a fourth input terminal and a second output terminal, the third input terminal being configured to receive an input signal associated with a first current flowing through a primary winding of a power converter, the second output terminal configured to output a second amplified signal to a fourth transistor terminal of a second transistor, the second transistor further including a fifth transistor terminal and a sixth transistor terminal, and the fourth input terminal being coupled to the sixth transistor terminal;

a current mirror including a first mirror terminal and a second mirror terminal, the first mirror terminal being coupled to the second transistor terminal;

a switch including a first switch terminal and a second switch terminal, the first switch terminal being coupled to the second mirror terminal, the second switch terminal being coupled to the fifth transistor terminal;

a first resistor including a first resistor terminal and a second resistor terminal, the first resistor being associated with a first resistance, the first resistor terminal being coupled to the second input terminal; and

a second resistor including a third resistor terminal and a fourth resistor terminal, the second resistor being associated with a second resistance, the third resistor terminal being coupled to the fourth input terminal;

wherein;

the first resistance is larger than the second resistance in magnitude; and

the error amplifier is configured to output a first output signal based at least in part on the reference signal and the input signal.

2. The error amplifier of claim 1 wherein the second operational amplifier is configured to receive a clock signal, and change the second amplified signal at the second output terminal in response to the clock signal.

3. The error amplifier of claim 1 wherein:

the error amplifier is coupled to a line-voltage compensator; and

the line-voltage compensator is configured to affect the input signal to keep an output current of the power converter approximately constant in response to an input voltage received by the power converter varying within a range.

4. The error amplifier of claim 3 wherein:

the error amplifier is coupled to a signal generator;

the line-voltage compensator is coupled to a first controller terminal and a second controller terminal;

the first controller terminal is configured to receive a first voltage associated with a second current, the second current being related to an input voltage of the power converter;

the line-voltage compensator is further configured to, in response to the first voltage satisfying one or more first conditions, generate a compensation current based at least in part on the second current;

the second controller terminal is configured to provide a compensation voltage based at least in part on the compensation current, the compensation voltage being equal in magnitude to the compensation current multiplied by a compensation resistance, the compensation resistance being associated with a compensation resistor;

the signal generator is configured to receive a second voltage and generate a second output signal, the second voltage being equal to a sum of a third voltage and the compensation voltage in magnitude, the third voltage being proportional to the first current flowing through the primary winding of the power converter; and

the third input terminal is further configured to receive the second output signal.

5. The error amplifier of claim 1 wherein:

the error amplifier is coupled to a load-signal compensator; and

the load-signal compensator is configured to affect the input signal to keep an output current of the power converter approximately constant if an output voltage of the power converter varies within a range.

6. The error amplifier of claim 5 wherein:

the error amplifier is coupled to a signal generator;

the load-signal compensator is coupled to a first controller terminal and a second controller terminal;

the first controller terminal is configured to receive a feedback signal associated with an output voltage of the power converter;

the load-signal compensator is further configured to sample the feedback signal during a demagnetization process of the power converter and generate a compensation current based at least in part on the sampled feedback signal;

the second controller terminal is configured to provide a compensation voltage based at least in part on the compensation current, the compensation voltage being equal in magnitude to the compensation current multiplied by a compensation resistance, the compensation resistance being associated with a compensation resistor;

the signal generator is configured to receive an input voltage and generate a second output signal, the input voltage being equal to a sum of a first voltage and the compensation voltage in magnitude, the first voltage being proportional to the first current flowing through the primary winding of the power converter; and

the third input terminal is further configured to receive the second output signal.

7. The error amplifier of claim 5 wherein:

the load-signal compensator is coupled to a first controller terminal and a second controller terminal;

the first controller terminal is configured to receive a feedback signal associated with an output voltage of the power converter;

the load-signal compensator is further configured to sample the feedback signal during a demagnetization process of the power converter and generate a compensation signal based at least in part on the sampled feedback signal;

the error amplifier is coupled to a third controller terminal;

the third controller terminal is configured to provide the second output terminal;

a second output signal is equal to a difference between a third amplified signal and the compensation signal in magnitude; and

the third amplified signal is related to a difference between the input signal and the reference signal in magnitude.

8. The error amplifier of claim 1 wherein the switch is configured to receive a demagnetization signal and be closed or opened in response to the demagnetization signal.

9. The error amplifier of claim 1 wherein the switch is configured to be closed during a demagnetization period associated with the power converter.

10. The error amplifier of claim 1 wherein the switch is configured to be opened before and after a demagnetization period associated with the power converter.

11. The error amplifier of claim 8 wherein the error amplifier is further configured to output the first output signal based at least in part on the reference signal, the input signal, and the demagnetization signal.

12. The error amplifier of claim 1 wherein:

the current mirror includes;

a third transistor including a seventh transistor terminal, an eighth transistor terminal and a ninth transistor terminal; and

a fourth transistor including a tenth transistor terminal, an eleventh transistor terminal and a twelfth transistor terminal;

wherein;

the seventh transistor terminal is coupled to the ninth transistor terminal and the tenth transistor terminal;

the eighth transistor terminal is coupled to the eleventh transistor terminal; and

the ninth transistor terminal is coupled to the second transistor terminal.

13. The error amplifier of claim 12 wherein the twelfth transistor terminal is coupled to the first switch terminal.

14. The error amplifier of claim 12 wherein:

the current mirror further includes;

a fifth transistor including a thirteenth transistor terminal, a fourteenth transistor terminal and a fifteenth transistor terminal; and

a third operational amplifier including a fifth input terminal, a sixth input terminal and a third output terminal;

wherein;

the thirteenth transistor terminal is coupled to the third output terminal;

the fourteenth transistor terminal is coupled to the twelfth transistor terminal and the fifth input terminal;

the fifteenth transistor terminal is coupled to the first switch terminal; and

the sixth input terminal is coupled to the ninth transistor terminal and the second transistor terminal.