Electronic latch, a method for an electronic latch, a frequency division by two and a 4-phase generator

• US 10,177,748 B2
• Filed: 12/02/2014
• Issued: 01/08/2019
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Bagger, Reza
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US15/524,375
• Publication Number:
  US 20180287594A1
• Time in Patent Office: 1,498 Days
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 23/425 using bistables
• CPC Class Codes: H03K 23/483 with a base which is an odd number
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 3/37 by the use, as active elements, of gas-filled tubes, e.g. astable trigger circuits H03K3/55 takes precedence
• CPC Class Codes: H03K 5/15066 using bistable devices H03K5/15093 takes precedence
• CPC Class Codes: H04B 1/40 Circuits

Abstract

The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state; The input circuit is further configured to select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state.

Claims

1. A four phase generator for generating four phase signals, comprising a first and a second electronic latch circuit, wherein the first and the second electronic latch circuit each comprises:

an output circuit, comprising;

an output X; and

an output Y;

an input circuit, comprising;

an input A

an input B

a clock signal input

wherein the input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of;

a first state comprising output of a high state at the output X, and output of a low state at the output Y;

a second state comprising output of a high state at the output X and at the output Y;

a third state comprising output of output of a low state at the output X and a high state at the output Y;

wherein the input circuit is further configured to;

select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state;

select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state;

select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state;

select the second state upon detecting a high state on the input B, a low state on the input A, a low state on the clock signal input, and that the electronic latch circuit is in the third state; and

wherein the four phase generator further comprises means for receiving a first clock signal at the clock signal input of the first electronic latch circuit, the four phase generator further comprises means for receiving a second clock signal at the clock signal input of the second electronic latch circuit, wherein the second clock signal is the inverse of the first clock signal, wherein the input A of the first electronic latch circuit is connected to the output X of the second electronic latch circuit, the input B of the first electronic latch circuit is connected to the output Y of the second electronic latch, the input A of the second electronic latch circuit is connected to the output Y of the first electronic latch circuit, and the input B of the second electronic latch circuit is connected to the output X of the first electronic latch, wherein a first phase signal is provided at the output X of the first electronic latch circuit, a second phase signal is provided at the output Y of the first electronic latch circuit, a third phase signal is provided at the output X′

of the second electronic latch circuit, and a fourth phase signal is provided at the output Y′

of the second electronic latch circuit, wherein in each of the first and second electronic latch circuits;

the input circuit comprises a first P-MOS transistor with a gate connected to the input A, and a second P-MOS transistor with a gate connected to the input B, a source of the first P-MOS transistor and a source of the second P-MOS transistor are connected to a supply voltage, a drain of the first P-MOS transistor is connected to a first node of the output circuit, and a source of the second P-MOS transistor is connected a second node of the output circuit,

the input circuit comprises a third N-MOS transistor with a gate connected to the clock signal input, a source connected to a second voltage potential, and a drain connected to the output circuit, and

the output circuit comprises a regenerative device connected to the first node and to the output X, the regenerative device is further connected to the second node and to the output Y, the regenerative device further comprises a third node connected to the input circuit, the regenerative device comprises a fourth N-MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node, the regenerative device further comprises a fifth N-MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node.