Omnibus logic element

• US 10,177,766 B1
• Filed: 11/14/2016
• Issued: 01/08/2019
• Est. Priority Date: 03/25/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Schleicher, James, Yuan, Richard, Pedersen, Bruce, Kaptanoglu, Sinan, Baeckler, Gregg, Lewis, David, Hutton, Mike, Lee, Andy L., Saini, Rahul, Kim, Henry
• Primary Examiner(s): A, Minh D
• Assistant Examiner(s): Cho, James H
• Application Number:
  US15/351,167
• Time in Patent Office: 785 Days
• Field of Search: None
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/50 Adding; Subtracting G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Claims

1. An apparatus, comprising:

an array of logic circuits, comprising;

a plurality of inputs;

a first plurality of look-up tables (“

LUTs”

) which receive at least a first portion of the plurality of inputs and a second plurality of LUTs which receive at least a second portion of the plurality of inputs

a first plurality of multiplexers (“

MUXs”

) which are programmatically driven by at least a portion of the first plurality of LUTs and a second plurality of MUXs which are programmatically driven by at least a portion of the second plurality of LUTs, wherein at least one of the first plurality of MUXs comprises an inverting input;

a carry in input, coupled to a carry out output of an adjacent logic circuit;

a carry out output, coupled to a carry in input of an adjacent logic circuit;

a first adder, coupled to selectively receive an input from at least one of the first plurality of LUTs; and

a second adder, coupled to selectively receive an input from at least one of the second plurality of LUTs,

wherein the first and second adders are coupled to enable the first adder to be cascaded with the second adder.

2. The apparatus of claim 1, wherein a portion of the array of logic circuits is selectively configurable to implement a 3:

2 compressor to facilitate addition of three n-bit inputs X, Y, and Z.

3. The apparatus of claim 2, wherein each of multiple respective LUTs is configured to receive a set of three binary input bits X, Y, and Z corresponding to a respective bit among the n-bits.

4. The apparatus of claim 3, wherein each of the multiple respective LUTs is configured to output a binary value corresponding to an addition results of the plurality of input bits X, Y, and Z.

5. The apparatus of claim 4, wherein each of a first portion of the multiple respective LUTs has an output that is coupled to an adder in a same logic circuit including the LUT, and each of a second portion of the multiple respective LUTs has an output that is coupled to an adder in a different logic circuit than a logic circuit including the LUT.

6. The apparatus of claim 1, wherein a first portion of the adders are coupled to a carry in a carry in input received from an adjacent logic circuit as a carry out output, and a second portion of the adders are coupled to a carry out a carry out output to be received as a carry inn input by an adjacent logic circuit.

7. The apparatus of claim 1, wherein the apparatus comprises a Field Programmable Gate Array (FPGA).

8. The apparatus of claim 1, wherein the multiple logic circuits comprises a logic element in a configurable logic block (CLB).

9. An apparatus, comprising:

a plurality of configurable logic blocks (CLBs), each of at least a portion of the plurality of configurable CLBs including,

a plurality of inputs;

a first adder;

a second adder;

a first plurality of look-up tables (“

LUTs”

) which receive at least a first portion of the plurality of inputs and a second plurality of LUTs which receive at least a second portion of the plurality of inputs;

a first plurality of multiplexers (“

MUXs”

) which are programmatically driven by at least a portion of the first plurality of LUTs to programmatically provide a first signal to the first adder and a second plurality of MUXs which are programmatically driven by at least a portion of the second plurality of LUTs to programmatically provide a second signal to the second adder, wherein at least one of the first plurality of MUXs comprises an inverting input;

a carry coupled between the first and second adders to cascade functionality of the first and second adders;

a carry in input, coupled to a carry out output of an adjacent CLB; and

a carry out output, coupled to a carry in input of an adjacent CLB.

10. The apparatus of claim 9, wherein at least one CLB is selectively configurable to implement a 3:

2 compressor to facilitate addition of three n-bit inputs X, Y, and Z.

11. The apparatus of claim 10, wherein each of multiple respective LUTs in the at least one CLB is configured to receive a set of three binary input bits X, Y, and Z corresponding to a respective bit among the n-bits.

12. The apparatus of claim 11, wherein each of the multiple respective LUTs is configured to output a binary value corresponding to an addition results of the plurality of input bits X, Y, and Z.

13. The apparatus of claim 12, wherein each of a first portion of the multiple respective LUTs has an output that is coupled to a first adder in a same logic circuit including the LUT, and each of a second portion of the multiple respective LUTs has an output that is coupled to a second adder in a different logic circuit than a logic circuit including the LUT.

14. The apparatus of claim 9, wherein the apparatus comprises a Field Programmable Gate Array (FPGA).

15. The apparatus of claim 9, wherein the apparatus comprises a Programmable Logic Device (PLD).