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Omnibus logic element

  • US 10,177,766 B1
  • Filed: 11/14/2016
  • Issued: 01/08/2019
  • Est. Priority Date: 03/25/2004
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • an array of logic circuits, comprising;

    a plurality of inputs;

    a first plurality of look-up tables (“

    LUTs”

    ) which receive at least a first portion of the plurality of inputs and a second plurality of LUTs which receive at least a second portion of the plurality of inputsa first plurality of multiplexers (“

    MUXs”

    ) which are programmatically driven by at least a portion of the first plurality of LUTs and a second plurality of MUXs which are programmatically driven by at least a portion of the second plurality of LUTs, wherein at least one of the first plurality of MUXs comprises an inverting input;

    a carry in input, coupled to a carry out output of an adjacent logic circuit;

    a carry out output, coupled to a carry in input of an adjacent logic circuit;

    a first adder, coupled to selectively receive an input from at least one of the first plurality of LUTs; and

    a second adder, coupled to selectively receive an input from at least one of the second plurality of LUTs,wherein the first and second adders are coupled to enable the first adder to be cascaded with the second adder.

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