Circuit including a switched capacitor bridge and method

• US 10,177,781 B2
• Filed: 06/24/2013
• Issued: 01/08/2019
• Est. Priority Date: 06/24/2013
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Nervegna, Louis, Del Signore, Bruce
• Primary Examiner(s): Tran, Thienvu
• Assistant Examiner(s): Baxter, Brian K
• Application Number:
  US13/925,781
• Publication Number:
  US 20140375135A1
• Time in Patent Office: 2,024 Days
• Field of Search: 307109
• CPC Class Codes: G01D 5/24 by varying capacitance
• CPC Class Codes: G01N 27/26 by investigating electrochemical variables; by using electrolysis or electrophoresis
• CPC Class Codes: G01R 17/105 for measuring impedance or resistance
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: H03M 3/362 in feedback mode, e.g. by reducing the order of the modulator
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path
• CPC Class Codes: H03M 3/476 Non-linear conversion systems
• CPC Class Codes: H03M 3/496 Details of sampling arrangements or methods

Abstract

A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.

Claims

1. A method comprising:

selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle by activating selected ones of a first and second plurality of switches of a first switching circuit including;

a first switch coupled between the first voltage and the first input node;

a second switch coupled between the second voltage and the second input node;

a third switch coupled between the first voltage and the second input node; and

a fourth switch coupled between the second voltage and the first input node;

selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle;

activating selected ones of a third and fourth plurality of switches of a second switching circuit including;

a third plurality of switches to selectively couple the first output node to one of first and second output terminals; and

a fourth plurality of switches to selectively couple the second output node to one of the first and second output terminals; and

selectively integrating output signals on the first and second output nodes using an integrator circuit, wherein switching of the first and second output nodes by selectively coupling cancels mismatches in capacitances between capacitors of the capacitive bridge.

2. The method of claim 1, wherein selectively coupling the first and second input nodes to one of the first and second voltages and the first and second output nodes to one of the first and second output terminals on first and second phases of the clock cycle comprises a chopping operation adapted to cancel mismatch errors.

3. The method of claim 1, wherein, during the first phase, selectively coupling the first and second input nodes to the first and second voltages comprises:

closing a first switch to couple the first voltage to the first input node and a second switch to couple the second voltage to the second input node; and

opening a third switch between the second voltage and the first input node and a fourth switch between the first voltage and the second input node.

4. The method of claim 1, wherein, during the first phase, selectively coupling the first and second output nodes to the first and second output terminals comprises:

closing a first switch to couple the first output node to the first output terminal and a second switch to couple the second output node to the second output terminal; and

opening a third switch between the first output node and the second output terminal and a fourth switch between the second output node and the first output terminal.

5. The method of claim 1, wherein, during the second phase, selectively coupling the first and second input nodes to the second and first voltages comprises:

closing a first switch to couple the first voltage to the second input node and a second switch to couple the second voltage to the first input node; and

opening a third switch between the first voltage and the first input node and a fourth switch between the second voltage and the second input node.

6. The method of claim 1, wherein, during the second phase, selectively coupling the first and second output nodes to the second and first output terminals, respectively, comprises:

closing a first switch to couple the first output node to the second output terminal and a second switch to couple the second output node to the first output terminal; and

opening a third switch between the first output node and the first output terminal and a fourth switch between the second output node and the second output terminal.

7. A circuit comprising:

a capacitor bridge including a first input node, a second input node, a first output node, and a second output node;

a first switching circuit including a first plurality of switches and a second plurality of switches, the first switching circuit configured to couple first and second voltages to first and second input nodes, respectively, during a first phase of a clock cycle and to selectively couple the second and first voltages to the first and second input nodes, respectively, during a second phase of the clock cycle, the first switching circuit including;

a first switch of the first plurality of switches, the first switch coupled between the first voltage and the first input node;

a second switch of the second plurality of switches, the second switch coupled between the second voltage and the second input node;

a third switch of the first plurality of switches, the third switch coupled between the first voltage and the second input node; and

a fourth switch of the second plurality of switches, the fourth switch coupled between the second voltage and the first input node;

a second switching circuit including;

a third plurality of switches to selectively couple the first output node to one of first and second output terminals; and

a fourth plurality of switches to selectively couple the second output node to one of the first and second output terminals; and

an integrator circuit coupled to the first and second output nodes; and

wherein the first and second switching circuits operate during the first and second phases to perform a chop operation to cancel mismatch errors.

8. The circuit of claim 7, wherein the second switching circuit is configured to selectively couple the first and second output nodes to the first and second inputs of the integrator circuit, respectively, during the first phase, and to selectively couple the second and first output nodes to the first and second inputs of the integrator circuit, respectively, during the second phase.

9. The circuit of claim 8, wherein the second switching circuit comprises:

a first switch of the third plurality of switches, the first switch coupled between the first output node and the first output terminal;

a second switch of the fourth plurality of switches, the second switch coupled between the second output node and the second output terminal;

a third switch of the third plurality of switches, the third switch coupled between the first output node and the second output terminal; and

a fourth switch of the fourth plurality of switches, the fourth switch coupled between the second output node and the first output terminal.

10. The circuit of claim 7, wherein the integrator circuit is configured to implement a delta-sigma converter.

11. The circuit of claim 7, wherein the capacitor bridge comprises:

a first capacitor coupled between the first input node and the first output node;

a second capacitor coupled between the second input node and the second output node;

a first variable capacitor coupled between the first input node and the second output node;

a second variable capacitor coupled between the second input node and the first output node.

12. A circuit comprising:

a capacitor bridge including a first input node, a second input node, a first output node and a second output node;

a first plurality of switches to selectively couple a first voltage to one of the first and second input nodes;

a second plurality of switches to selectively couple a second voltage to one of the first and second input nodes;

a third plurality of switches to selectively couple the first output node to one of first and second output terminals; and

a fourth plurality of switches to selectively couple the second output node to one of the first and second output terminals.

13. The circuit of claim 12, wherein the first plurality of switches comprises:

a first switch configured to selectively couple the first voltage to the first input node; and

a second switch configured to selectively couple the first voltage to the second input node.

14. The circuit of claim 12, wherein the second plurality of switches comprises:

a first switch configured to selectively couple the second voltage to the second input node; and

a second switch configured to selectively couple the second voltage to the first input node.

15. The circuit of claim 12, wherein:

the third plurality of switches comprises;

a first switch configured to selectively couple the first output node to the first output terminal; and

a second switch configured to selectively couple the first output node to the second output terminal; and

the fourth plurality of switches comprises;

a third switch configured to selectively couple the second output node to the second output terminal; and

a fourth switch configured to selectively couple the second output node to the first output terminal.

16. The circuit of claim 12, wherein, during a first phase of a clock cycle:

the first plurality of switches selectively couple the first voltage to the first input node;

the second plurality of switches selectively couple the second voltage to the second input node;

the third plurality of switches selectively couple the first output node to the first output terminal; and

the fourth plurality of switches selectively couple the second output node to the second output terminal.

17. The circuit of claim 16, wherein, during a second phase of the clock cycle:

the first plurality of switches selectively couple the first voltage to the second input node;

the second plurality of switches selectively couple the second voltage to the first input node;

the third plurality of switches selectively couple the first output node to the second output terminal; and

the fourth plurality of switches selectively couple the second output node to the first output terminal.