Memory device including current generator plate

• US 10,181,341 B1
• Filed: 09/07/2018
• Issued: 01/15/2019
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US16/125,315
• Publication Number:
  US 20190019540A1
• Time in Patent Office: 130 Days
• Field of Search: 36518518
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second conductive material located in a second level of the apparatus; pillars extending between the first and second levels and contacting the first and second conductive materials; memory cells located along the pillars; first select gates located in a third level of the apparatus between the first and second levels, with each of the first select gates being located along a segment of a respective pillar among the pillars; second select gates located in a fourth level of the apparatus between the first and third levels; and a conductive plate located in a fifth level of the apparatus between the first and fourth levels, with each of the pillars extending through the conductive plate.

Claims

1. An apparatus comprising:

a substrate;

a first deck of memory cells located over the substrate;

a second deck of memory cells located over the first deck of memory cell, each of the first and second decks of memory cells including;

a pillar extending between a first conductive material and a second conductive material, the pillar including a first segment, a second segment, a third segment, and a fourth segment, the second segment being between the first and third segments, and the third segment being between the second and fourth segments;

a memory cell string and control lines along the fourth segment of the pillar;

a first select gate including a first piece of material along the second segment of the pillar,

a second select gate including a second piece of material along the third segment of the pillar,

a conductive plate including a third piece of material in a level of between the first and second conductive lines, wherein the third piece of material is separated from each of the first and second pieces of materials by a dielectric; and

a dielectric between a portion of the conductive plate and the first segment of the pillar.

2. The apparatus of claim 1, wherein:

the first conductive material in the first deck of memory cells is part of a data line of the first deck of memory cells;

the second conductive material in the first deck of memory cells is part of a source of the first deck of memory cells;

the first conductive material in the second deck of memory cells is part of a data line of the second deck of memory cells; and

the second conductive material in the second deck of memory cells is part of a source of the second deck of memory cells.

3. The apparatus of claim 1, wherein the memory cells of the first deck of memory cells are organized in first blocks of memory cells, and the memory cells of the second deck of memory cells are organized in second block of memory cells.

4. The apparatus of claim 1, further comprising at least one additional deck of memory cells located over the second deck of memory cells.

5. The apparatus of claim 1, further comprising:

a first select line coupled to the first select gate; and

a second select line coupled to the second select gate, wherein the conductive plate has a thickness greater than a thickness of each of the first and second the select lines.

6. The apparatus of claim 1, wherein the conductive plate and the control lines are formed from different materials.

7. The apparatus of claim 1, wherein the conductive plate is formed from polycrystalline silicon.

8. The apparatus of claim 7, wherein the control lines are formed from metal.

9. An apparatus comprising:

a substrate;

data lines located in a first level of the apparatus over the substrate, the data lines having lengths extending in a first direction;

a conductive material located in a second level of the apparatus;

pillars extending between the first and second levels and contacting the data lines and the conductive material;

memory cells located along the pillars;

first select gates located in a third level of the apparatus between the first and second levels, each of the first select gates including a first piece of material located along a first segment of a respective pillar among the pillars;

second select gates located in a fourth level of the apparatus between the first and third levels, each of the second select gates including a second piece of material located in the fourth level of the apparatus between the first and third levels;

a first conductive plate located in a fifth level of the apparatus between the first and fourth levels and between the data lines and the conductive material, the first conductive plate having a length extending in a second direction; and

a second conductive plate located in the fifth level between the data lines and the conductive material and separated from the first conductive plate, the second conductive plate having a length extending in the second direction.

10. The apparatus of claim 9, wherein each of the first and second conductive plates is located immediately next to the data lines.

11. The apparatus of claim 9, further comprising a third conductive plate located in the fifth level between the data lines and the conductive material and separated from the first and second conductive plates, the third conductive plate having a length extending in the second direction.

12. The apparatus of claim 9, further comprising control lines located on levels where the memory cells are located, wherein each of the control lines is a metal control line.

13. The apparatus of claim 12, wherein each of the first and second conductive plates is formed from polycrystalline silicon.

14. The apparatus of claim 9, wherein the apparatus comprises a memory device, the memory device comprising multiple decks of memory cells located over the substrate, wherein the data lines, the conductive material, the pillars, the memory cells, the first select gates, the second select gates, the first conductive plate, and the second conductive plate are included in a deck of the deck of memory cells.

15. An apparatus comprising:

first conductive materials located in a first level of the apparatus;

a second conductive material located in a second level of the apparatus;

first pillars extending between the first and second levels and contacting the first and second conductive materials;

first memory cells located along the first pillars;

first select gates located in a third level of the apparatus between the first and second levels, each of the first select gates being located along a segment of a respective pillar among the first pillars;

second select gates located in a fourth level of the apparatus between the first and third levels;

a first conductive plate located in a fifth level of the apparatus between the first and fourth levels, each of the first pillars extending through the first conductive plate;

first additional conductive materials separated from the first conductive material and located in the first level of the apparatus;

a second additional conductive material located in the second level of the apparatus;

second pillars extending between the first and second levels and contacting the first and second additional conductive materials;

second memory cells located along the second pillars;

first additional select gates located in the third level of the apparatus, each of the first additional select gates being located along a segment of a respective pillar among the second pillars;

second additional select gates located in the fourth level of the apparatus; and

a second conductive plate located in the fifth level of the apparatus, each of the second pillars extending through the second conductive plate.

16. The apparatus of claim 15, wherein the first conductive materials are part of first data lines of the apparatus, and the first additional conductive materials are part of second data lines of the apparatus separated from the first data lines.

17. The apparatus of claim 15, wherein the second conductive material is part of a first source of the apparatus, and the second additional conductive material is part of a second source of the apparatus separated from the first source.

18. The apparatus of claim 15, wherein the first and second conductive plates are formed from polycrystalline silicon.

19. The apparatus of claim 15, wherein the first memory cells are organized in first blocks of memory cells, and the second memory cells are organized in second blocks of memory cells separated from the first blocks of memory cells.

20. The apparatus of claim 19, wherein the apparatus comprises a memory device, the memory device comprising multiple decks of memory cells located over the substrate, wherein the first blocks of memory cells are located in a first deck of the multiple decks of memory cells, and the second blocks of memory cells are located in a second deck of the multiple decks of memory cells.