Shift register and display device

• US 10,181,359 B2
• Filed: 10/23/2015
• Issued: 01/15/2019
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Miyake, Hiroyuki, Amano, Seiko
• Primary Examiner(s): Michaud, Robert
• Application Number:
  US14/921,073
• Publication Number:
  US 20160042807A1
• Time in Patent Office: 1,180 Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0285 using tables for spatial correction of display data
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.

Claims

1. A semiconductor device comprising:

a first to eleventh transistors each comprising a gate, a source and a drain,

wherein the gate of the first transistor is electrically connected to the gate of the second transistor,

wherein one of the source and the drain of the first transistor is directly connected to one of the source and the drain of the third transistor and one of the source and the drain of the fourth transistor,

wherein the gate of the third transistor is directly connected to one of the source and the drain of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to one of the source and the drain of the eighth transistor,

wherein one of the source and the drain of the second transistor is directly connected to one of the source and the drain of the ninth transistor, and

wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the tenth transistor and the gate of the eleventh transistor.

2. The semiconductor device according to claim 1, wherein the gate of the third transistor is directly connected to one of the source and the drain of the second transistor.

3. The semiconductor device according to claim 1, wherein the other of the source and the drain of the third transistor is directly connected to the other of the source and the drain of the second transistor, one of the source and the drain of the sixth transistor, and one of the source and the drain of the seventh transistor.

4. The semiconductor device according to claim 1, wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the eighth transistor, and the other of the source and the drain of the ninth transistor.

5. The semiconductor device according to claim 1, wherein at least one of the first to eleventh transistors comprises an oxide semiconductor layer serving as a channel formation layer.

6. A semiconductor device comprising:

a first to third clock signal lines, and

a first to eleventh transistors each comprising a gate, a source and a drain,

wherein the gate of the first transistor is directly connected to the gate of the second transistor,

wherein one of the source and the drain of the first transistor is directly connected to one of the source and the drain of the third transistor and one of the source and the drain of the fourth transistor,

wherein the gate of the third transistor is directly connected to one of the source and the drain of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to one of the source and the drain of the eighth transistor,

wherein one of the source and the drain of the second transistor is directly connected to one of the source and the drain of the ninth transistor,

wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the tenth transistor and the gate of the eleventh transistor,

wherein the first clock signal line is directly connected to one of the source and the drain of the tenth transistor and one of the source and the drain of the eleventh transistor,

wherein the second clock signal line is directly connected to the gate of the fifth transistor, and

wherein the third clock signal line is directly connected to the gate of the eighth transistor.

7. The semiconductor device according to claim 6, wherein the gate of the third transistor is directly connected to one of the source and the drain of the second transistor.

8. The semiconductor device according to claim 6, wherein the other of the source and the drain of the third transistor is directly connected to the other of the source and the drain of the second transistor, one of the source and the drain of the sixth transistor, and one of the source and the drain of the seventh transistor.

9. The semiconductor device according to claim 6, wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the eighth transistor, and the other of the source and the drain of the ninth transistor.

10. The semiconductor device according to claim 6, wherein at least one of the first to eleventh transistors comprises an oxide semiconductor layer serving as a channel formation layer.

11. A semiconductor device comprising:

a first to eighth flip-flops, and

a first to eighth clock signal lines,

wherein the first to third clock signal lines are electrically connected to the first flip-flop,

wherein the second to fourth clock signal lines are electrically connected to the second flip-flop,

wherein the third to fifth clock signal lines are electrically connected to the third flip-flop,

wherein the fourth to sixth clock signal lines are electrically connected to the fourth flip-flop,

wherein the fifth to seventh clock signal lines are electrically connected to the fifth flip-flop,

wherein the sixth to eighth clock signal lines are electrically connected to the sixth flip-flop,

wherein the seventh, the eighth, and the first clock signal lines are electrically connected to the seventh flip-flop,

wherein the eighth, the first, and the second clock signal lines are electrically connected to the eighth flip-flop,

wherein the first flip-flop comprises a first to eleventh transistors each comprising a gate, a source and a drain,

wherein the gate of the first transistor is electrically connected to the gate of the second transistor,

wherein one of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor and one of the source and the drain of the fourth transistor,

wherein the gate of the third transistor is electrically connected to one of the source and the drain of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the eighth transistor,

wherein one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the ninth transistor, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the tenth transistor and the gate of the eleventh transistor.

12. The semiconductor device according to claim 11, wherein the gate of the third transistor is electrically connected to one of the source and the drain of the second transistor.

13. The semiconductor device according to claim 11, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, one of the source and the drain of the sixth transistor, and one of the source and the drain of the seventh transistor.

14. The semiconductor device according to claim 11, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the eighth transistor, and the other of the source and the drain of the ninth transistor.

15. The semiconductor device according to claim 11, wherein at least one of the first to eleventh transistors comprises an oxide semiconductor layer serving as a channel formation layer.