Microelectronic package for wafer-level chip scale packaging with fan-out

• US 10,181,457 B2
• Filed: 10/24/2016
• Issued: 01/15/2019
• Est. Priority Date: 10/26/2015
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Prabhu, Ashok S., Katkar, Rajesh
• Primary Examiner(s): Zarneke, David A
• Application Number:
  US15/332,991
• Publication Number:
  US 20170117260A1
• Time in Patent Office: 813 Days
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4885 Wire-like parts or pins wire ball formation B23K20/00; methods related to connecting semiconductor or other solid state bodies H01L24/00
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/60 Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1533 : the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

Claims

1. A package-on-package device for wafer-level chip scale packaging with fan-out, comprising:

a metal substrate having an upper surface and a lower surface opposite the upper surface;

the substrate including outer conductive pads and inner conductive pads formed therein from material of the substrate electrically isolated from one another and from a remainder of the substrate;

lower ends of wire bond wires directly coupled to the outer conductive pads along the upper surface for electrical conductivity between the wire bond wires and the outer conductive pads associated therewith;

lower ends of first interconnects directly coupled to the inner conductive pads along the upper surface for electrical conductivity between the first interconnects and the inner conductive pads;

a redistribution layer having second interconnects coupled to the outer and the inner conductive pads along the lower surface for electrical conductivity between the outer and the inner conductive pads; and

a microelectronic device directly coupled to upper ends of the first interconnects for electrical conductivity, wherein the outer conductive pads are located outside of a perimeter of the microelectronic device for the fan-out from the inner conductive pads located below the microelectronic device.

2. The package-on-package device according to claim 1, wherein the remainder of the substrate is a ground plane.

3. The package-on-package device according to claim 1, wherein the redistribution layer is a first redistribution layer, the package-on-package device further comprising a second redistribution layer with a bottom surface thereof interconnected to upper ends of the wire bond wires for electrical conductivity.

4. The package-on-package device according to claim 3, wherein the microelectronic device is a first microelectronic device, the package-on-package device further comprising:

a second microelectronic device interconnected to a top surface of the second redistribution layer for electrical conductivity to the upper ends of the wire bond wires through the second redistribution layer; and

wherein the first interconnects are posts.

5. The package-on-package device according to claim 1, further comprising a molding material layer disposed around the posts and the microelectronic device.

6. The package-on-package device according to claim 5, wherein the molding material layer is a first molding material layer, the package-on-package device further comprising a second molding material layer disposed around the wire bond wires.