Memory cell comprising first and second transistors and methods of operating

• US 10,181,471 B2
• Filed: 04/12/2017
• Issued: 01/15/2019
• Est. Priority Date: 02/16/2012
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Han, Jin-Woo, Louie, Benjamin S.
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US15/485,718
• Publication Number:
  US 20170229466A1
• Time in Patent Office: 643 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/70 Bipolar devices
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Claims

1. A method of operating a semiconductor memory cell having a bi-stable floating body transistor having a first drain region and a first source region separated by a floating body region and an access transistor lacking a floating body region and having a second source region and a second drain region separated by a well region, wherein the floating body transistor is directly joined to the access transistor, the first source region is connected to a source line terminal through a first conductive element, and the second drain region is connected to a bit line terminal through a second conductive element, said method comprising:

applying voltage to the access transistor to turn on the access transistor; and

assisting selection of the memory cell for an operation by activating the access transistor.

2. The method of claim 1, wherein said operation is a read operation comprising monitoring current through the memory cell to sense a state of the floating body transistor.

3. The method of claim 1, wherein said operation is a write logic-1 operation, wherein the voltage applied to the access transistor is a positive bias applied to the bit line terminal, and wherein the access transistor passes said positive bias to the first drain region.

4. The method of claim 3, further comprising further biasing the floating body transistor to maximize hole generation through an impact ionization mechanism.

5. The method of claim 3, wherein the voltage applied to the access transistor is biased to cause the second source region to float, said method further comprising increasing potential of a floating body of the floating body region by capacitive coupling.

6. The method of claim 1, wherein said operation is a write logic-0 operation, wherein the voltage applied to the access transistor is a negative bias, and wherein the access transistor passes said negative bias to the first drain region.

7. The method of claim 1, wherein said operation is an active low read operation.

8. The method of claim 1, wherein said operation is an active low write logic-1 operation.

9. The method of claim 1, wherein said operation is a read operation comprising monitoring current through the memory cell to sense a state of the floating body transistor;

and wherein the voltage applied to turn on the access transistor is zero voltage.

10. The method of claim 1, wherein said operation is a write logic-1 operation, wherein the voltage applied to the access transistor comprises applying zero voltage to a word line terminal of the access transistor, and the write logic-1 operation is performed by a band-to-band tunneling mechanism.

11. The method of claim 1, wherein said operation is a write logic-1 operation, wherein the voltage applied to the access transistor comprises applying zero voltage to a word line terminal of the access transistor, and the write logic-1 operation is performed by through an impact ionization mechanism.

12. The method of claim 1, wherein said operation is a write logic-1 operation, and the voltage applied to the access transistor is a positive voltage biased to cause the second source region to float, said method further comprising increasing potential of a floating body of the floating body region by capacitive coupling.

13. The method of claim 1, wherein said operation is a write logic-0 operation, wherein the voltage applied to the access transistor is a positive bias applied to a word line terminal of the access transistor.

14. The method of claim 1, wherein said operation is a write logic-0 operation, wherein the voltage applied to a word line terminal of the access transistor is a negative bias that is more negative than a negative bias applied to the first drain region.