Radio frequency switch having field effect transistor cells
First Claim
1. An electronic component comprising a plurality of field-effect transistor (FET) cells that form a first transistor over a semiconductor substrate, wherein each FET cell of the plurality of FET cells comprises:
- a finger region having a rectangular shape with a first end, a second end, and first sides comprising;
a drain finger disposed over the semiconductor substrate along a drain axis that is in parallel with the first sides;
a source finger spaced from the drain finger and disposed over the semiconductor substrate along a source axis that is in parallel with the first sides;
a gate finger disposed over the semiconductor substrate such that the gate finger is spaced between and in parallel with the drain finger and the source finger, wherein the finger region has a first non-linear off-state capacitance that increases as drain-to-source voltage increases within a first voltage range;
an isolation region that extends across the first end of the finger region;
an off-state linearization region having a rectangular shape with a third end that abuts the isolation region and a fourth end and second sides comprising;
a doped well that is disposed over the semiconductor substrate and extending between the second sides from the third end to the fourth end;
a dielectric layer disposed over the doped well;
a first conductive stripe disposed over the dielectric layer between the third end and the fourth end in longitudinal alignment with the drain axis;
a second conductive stripe disposed over the dielectric layer between the third end and the fourth end in longitudinal alignment with the source axis;
a drain finger electrode aligned over and coupled to both the drain finger and first conductive stripe; and
a source finger electrode aligned over and coupled to both the source finger and the second conductive stripe, wherein the off-state linearization region has a second non-linear off-state capacitance that decreases as the drain-to-source voltage increases within the first voltage range.
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Accused Products
Abstract
An electronic component made up of field-effect transistor (FET) cells is disclosed. Each FET cell includes a finger region having drain, gate, and source fingers disposed over a semiconductor substrate. An isolation region extends across a first end of the finger region. An off-state linearization region abuts the first end of the isolation region. A doped well is disposed within the off-state linearization region over the semiconductor substrate. A dielectric layer is disposed over the doped region. A first conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A second conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A drain finger electrode is aligned over and coupled to both the drain finger and the first conductive stripe. A source finger electrode is aligned over and coupled to both the source finger and the second conductive stripe.
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Citations
20 Claims
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1. An electronic component comprising a plurality of field-effect transistor (FET) cells that form a first transistor over a semiconductor substrate, wherein each FET cell of the plurality of FET cells comprises:
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a finger region having a rectangular shape with a first end, a second end, and first sides comprising; a drain finger disposed over the semiconductor substrate along a drain axis that is in parallel with the first sides; a source finger spaced from the drain finger and disposed over the semiconductor substrate along a source axis that is in parallel with the first sides; a gate finger disposed over the semiconductor substrate such that the gate finger is spaced between and in parallel with the drain finger and the source finger, wherein the finger region has a first non-linear off-state capacitance that increases as drain-to-source voltage increases within a first voltage range; an isolation region that extends across the first end of the finger region; an off-state linearization region having a rectangular shape with a third end that abuts the isolation region and a fourth end and second sides comprising; a doped well that is disposed over the semiconductor substrate and extending between the second sides from the third end to the fourth end; a dielectric layer disposed over the doped well; a first conductive stripe disposed over the dielectric layer between the third end and the fourth end in longitudinal alignment with the drain axis; a second conductive stripe disposed over the dielectric layer between the third end and the fourth end in longitudinal alignment with the source axis; a drain finger electrode aligned over and coupled to both the drain finger and first conductive stripe; and a source finger electrode aligned over and coupled to both the source finger and the second conductive stripe, wherein the off-state linearization region has a second non-linear off-state capacitance that decreases as the drain-to-source voltage increases within the first voltage range. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification