Semiconductor devices and methods of forming the same

• US 10,181,525 B2
• Filed: 12/09/2016
• Issued: 01/15/2019
• Est. Priority Date: 09/21/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Roh, Donghyun, Park, Pankwi, Shin, Dongsuk, Lee, Chulwoong, Lee, Nae-in
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US15/374,093
• Publication Number:
  US 20170092769A1
• Time in Patent Office: 767 Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Claims

1. A semiconductor device comprising:

a substrate;

a gate dielectric layer on the substrate;

a gate electrode on the gate dielectric layer, the gate electrode including at least one sidewall;

a first spacer on the at least one sidewall of the gate electrode, a second spacer on the first spacer, and a third spacer on the second spacer; and

a protecting insulating layer disposed between the third spacer and the substrate,

wherein a portion of the protecting insulating layer is disposed between the first spacer and the third spacer.

2. The semiconductor device of claim 1, wherein the protecting insulating layer is disposed on the third spacer and the gate electrode.

3. The semiconductor device of claim 1, further comprising a stress pattern disposed in the substrate and adjacent to the gate electrode.

4. The semiconductor device of claim 3, wherein the protecting insulating layer is disposed on the stress pattern.

5. The semiconductor device of claim 1, wherein a top surface of the second spacer is at a height from the substrate that is greater than half of a height that the gate electrode extends from the substrate.

6. The semiconductor device of claim 1, wherein the protecting insulating layer comprises at least one of a silicon oxide and silicon nitride.

17. The semiconductor device of claim 1, wherein the third spacer comprises a first insulating material, and the protecting insulating layer comprises a second insulating material different from the first insulating material.

18. The semiconductor device of claim 17, wherein the second spacer comprises a third insulating material different from the first insulating material.

19. The semiconductor device of claim 18, wherein the first spacer comprises the first insulating material.

20. The semiconductor device of claim 1, wherein the protecting insulating layer is between the second spacer and the substrate.

7. A semiconductor device comprising:

a substrate;

a gate dielectric layer on the substrate;

a gate electrode on the gate dielectric layer, the gate electrode including at least one sidewall;

a first spacer on the at least one sidewall of the gate electrode, a second spacer on the first spacer, and a third spacer on the second spacer;

a gap region formed under the second spacer; and

a protecting insulating layer filling the gap region.

8. The semiconductor device of claim 7, wherein the protecting insulating layer is disposed on the third spacer and the gate electrode.

9. The semiconductor device of claim 7, further comprising a stress pattern disposed in the substrate and adjacent to the gate electrode.

10. The semiconductor device of claim 9, wherein the protecting insulating layer is disposed on the stress pattern.

11. The semiconductor device of claim 7, wherein a top surface of the second spacer is at a height from the substrate that is greater than half of a height that the gate electrode extends from the substrate.

12. The semiconductor device of claim 7, wherein the protecting insulating layer comprises at least one of a silicon oxide and silicon nitride.

13. A semiconductor device comprising:

a substrate;

a gate dielectric layer on the substrate;

a gate electrode on the gate dielectric layer, the gate electrode including at least one sidewall;

a first spacer on the at least one sidewall of the gate electrode, a second spacer on the first spacer, and a third spacer on the second spacer;

a gap region between the first spacer and the third spacer; and

a stress pattern in the substrate adjacent to the gate electrode.

14. The semiconductor device of claim 13, further comprising a protecting pattern filling the gap region.

15. The semiconductor device of claim 14, wherein the protecting pattern comprises at least one of a silicon oxide and silicon nitride.

16. The semiconductor device of claim 13, wherein a top surface of the second spacer is at a height from the substrate that is greater than half of a height that the gate electrode extends from the substrate.

21. A semiconductor device comprising:

a substrate;

a gate dielectric layer on the substrate;

a gate electrode on the gate dielectric layer, the gate electrode including at least one sidewall;

a first spacer on the at least one sidewall of the gate electrode, a second spacer on the first spacer, and a third spacer on the second spacer; and

a protecting insulating layer disposed between the third spacer and the substrate, the protecting insulating layer directly contacting a bottom surface of the third spacer.

22. The semiconductor device of claim 21, wherein the third spacer comprises a first insulating material, and the protecting insulating layer comprises a second insulating material different from the first insulating material.

23. The semiconductor device of claim 21, wherein the protecting insulating layer is disposed on the third spacer and the gate electrode.

24. The semiconductor device of claim 21, further comprising a stress pattern disposed in the substrate and adjacent to the gate electrode.

25. The semiconductor device of claim 21, wherein the protecting insulating layer is between the second spacer and the substrate.

26. The semiconductor device of claim 21, wherein a portion of the protecting insulating layer is disposed between the first spacer and the third spacer.