Semiconductor device
First Claim
Patent Images
1. A semiconductor device comprising:
- a first circuit in an odd number stage; and
a second circuit in an even number stage,wherein the first circuit includes first to ninth transistors,wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor,wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the second transistor,wherein a gate of the second transistor is electrically connected to the other of the source and the drain of the second transistor,wherein a gate of the third transistor is electrically connected to a second wiring,wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor,wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor,wherein a gate of the fifth transistor is electrically connected to a gate of the fourth transistor,wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the fourth transistor,wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor,wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the fourth transistor,wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor,wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor,wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor,wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor,wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fourth transistor,wherein a gate of the ninth transistor is electrically connected to the gate of the first transistor,wherein the second circuit includes tenth to eighteenth transistors,wherein one of a source and a drain of the tenth transistor is electrically connected to a third wiring,wherein one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor,wherein the other of the source and the drain of the eleventh transistor is electrically connected to the other of the source and the drain of the twelfth transistor,wherein a gate of the tenth transistor is electrically connected to the one of the source and the drain of the eleventh transistor,wherein a gate of the eleventh transistor is electrically connected to the other of the source and the drain of the eleventh transistor,wherein a gate of the twelfth transistor is electrically connected to a fourth wiring,wherein one of a source and a drain of the thirteenth transistor is electrically connected to the other of the source and the drain of the tenth transistor,wherein one of a source and a drain of the fourteenth transistor is electrically connected to the gate of the tenth transistor,wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor,wherein a gate of the fourteenth transistor is electrically connected to a gate of the thirteenth transistor,wherein one of a source and a drain of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor,wherein one of a source and a drain of the sixteenth transistor is electrically connected to the gate of the thirteenth transistor,wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor,wherein a gate of the sixteenth transistor is electrically connected to the gate of the tenth transistor,wherein one of a source and a drain of the seventeenth transistor is electrically connected to a gate of the fifteenth transistor,wherein the other of the source and the drain of the seventeenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor,wherein a gate of the seventeenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor,wherein one of a source and a drain of the eighteenth transistor is electrically connected to the gate of the fifteenth transistor,wherein the other of the source and the drain of the eighteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor,wherein a gate of the eighteenth transistor is electrically connected to the gate of the tenth transistor,wherein a first clock signal is input to the first wiring,wherein a second clock signal is input to the second wiring,wherein a third clock signal is input to the third wiring,wherein a fourth clock signal is input to said fourth wiring.
1 Assignment
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Accused Products
Abstract
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.
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Citations
2 Claims
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1. A semiconductor device comprising:
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a first circuit in an odd number stage; and a second circuit in an even number stage, wherein the first circuit includes first to ninth transistors, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the second transistor, wherein a gate of the second transistor is electrically connected to the other of the source and the drain of the second transistor, wherein a gate of the third transistor is electrically connected to a second wiring, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the fifth transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the fourth transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor, wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor, wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor, wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the ninth transistor is electrically connected to the gate of the first transistor, wherein the second circuit includes tenth to eighteenth transistors, wherein one of a source and a drain of the tenth transistor is electrically connected to a third wiring, wherein one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor, wherein the other of the source and the drain of the eleventh transistor is electrically connected to the other of the source and the drain of the twelfth transistor, wherein a gate of the tenth transistor is electrically connected to the one of the source and the drain of the eleventh transistor, wherein a gate of the eleventh transistor is electrically connected to the other of the source and the drain of the eleventh transistor, wherein a gate of the twelfth transistor is electrically connected to a fourth wiring, wherein one of a source and a drain of the thirteenth transistor is electrically connected to the other of the source and the drain of the tenth transistor, wherein one of a source and a drain of the fourteenth transistor is electrically connected to the gate of the tenth transistor, wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to a gate of the thirteenth transistor, wherein one of a source and a drain of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor, wherein one of a source and a drain of the sixteenth transistor is electrically connected to the gate of the thirteenth transistor, wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the gate of the tenth transistor, wherein one of a source and a drain of the seventeenth transistor is electrically connected to a gate of the fifteenth transistor, wherein the other of the source and the drain of the seventeenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor, wherein a gate of the seventeenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor, wherein one of a source and a drain of the eighteenth transistor is electrically connected to the gate of the fifteenth transistor, wherein the other of the source and the drain of the eighteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor, wherein a gate of the eighteenth transistor is electrically connected to the gate of the tenth transistor, wherein a first clock signal is input to the first wiring, wherein a second clock signal is input to the second wiring, wherein a third clock signal is input to the third wiring, wherein a fourth clock signal is input to said fourth wiring.
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2. A semiconductor device comprising:
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a gate driver, wherein the gate driver includes first to ninth transistors, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor, wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the second transistor, wherein a gate of the second transistor is electrically connected to the other of the source and the drain of the second transistor, wherein a gate of the third transistor is electrically connected to a second wiring, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the first transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the fifth transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the fourth transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor, wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor, wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the sixth transistor, wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein a gate of the ninth transistor is electrically connected to the gate of the first transistor, wherein the gate driver includes tenth to eighteenth transistors, wherein one of a source and a drain of the tenth transistor is electrically connected to a third wiring, wherein one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor, wherein the other of the source and the drain of the eleventh transistor is electrically connected to the other of the source and the drain of the twelfth transistor, wherein a gate of the tenth transistor is electrically connected to the one of the source and the drain of the eleventh transistor, wherein a gate of the eleventh transistor is electrically connected to the other of the source and the drain of the eleventh transistor, wherein a gate of the twelfth transistor is electrically connected to a fourth wiring, wherein one of a source and a drain of the thirteenth transistor is electrically connected to the other of the source and the drain of the tenth transistor, wherein one of a source and a drain of the fourteenth transistor is electrically connected to the gate of the tenth transistor, wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to a gate of the thirteenth transistor, wherein one of a source and a drain of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor, wherein one of a source and a drain of the sixteenth transistor is electrically connected to the gate of the thirteenth transistor, wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the gate of the tenth transistor, wherein one of a source and a drain of the seventeenth transistor is electrically connected to a gate of the fifteenth transistor, wherein the other of the source and the drain of the seventeenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor, wherein a gate of the seventeenth transistor is electrically connected to the other of the source and the drain of the fifteenth transistor, wherein one of a source and a drain of the eighteenth transistor is electrically connected to the gate of the fifteenth transistor, wherein the other of the source and the drain of the eighteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor, wherein a gate of the eighteenth transistor is electrically connected to the gate of the tenth transistor, wherein a first clock signal is input to the first wiring, wherein a second clock signal is input to the second wiring, wherein a third clock signal is input to the third wiring, wherein a fourth clock signal is input to said fourth wiring.
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsUmezaki, Atsushi
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Primary Examiner(s)Ma, Calvin C
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Application NumberUS16/022,806Publication NumberTime in Patent Office200 DaysField of Search345 87, 345205, 345690US Class CurrentCPC Class CodesG09G 2300/04 Structural and physical det...G09G 2310/0275 Details of drivers for data...G09G 3/20 for presentation of an asse...G09G 3/3648 using an active matrix G09G...G11C 19/28 using semiconductor element...H01L 21/477 Thermal treatment for modif...H01L 27/1255 integrated with passive dev...H01L 27/127 with a particular formation...H01L 29/7869 having a semiconductor body...
