Gain level control circuit supporting dynamic gain control in a wireless communications system (WCS)
First Claim
1. A gain level control circuit in a wireless communications system (WCS), comprising:
- a digital signal distribution circuit comprising a plurality of digital signal inputs and a plurality of digital signal outputs, the digital signal distribution circuit configured to;
receive a plurality of first digital communications signals having a plurality of first digital amplitudes from the plurality of digital signal inputs, respectively; and
generate a plurality of second digital communications signals having a plurality of second digital amplitudes at the plurality of digital signal outputs based on the plurality of first digital communications signals, wherein each of the plurality of second digital amplitudes is represented up to a full-scale digital amplitude in a predefined number of binary bits; and
a digital signal processing circuit coupled to the plurality of digital signal inputs, the digital signal processing circuit configured to;
determine that a selected second digital communications signal among the plurality of second digital communications signals has a selected second digital amplitude among the plurality of second digital amplitudes approaching the full-scale digital amplitude that can be represented by the predefined number of binary bits;
determine a selected first digital communications signal among the plurality of first digital communications signals having a selected first digital amplitude causing the selected second digital amplitude to approach the full-scale digital amplitude; and
control the digital signal distribution circuit to adjust the selected first digital amplitude to reduce the selected second digital amplitude.
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Accused Products
Abstract
A gain level control circuit in a wireless distribution system (WDS) is provided. The digital level control circuit receives a number of first digital communications signals having a number of first digital amplitudes and generates a number of second digital communications signals having a number of second digital amplitudes. When a selected second digital amplitude approaches a full-scale digital amplitude represented by a predefined number of binary bits, the gain level control circuit determines a selected first digital communications signal having a selected first digital amplitude causing the selected second digital amplitude to exceed the full-scale digital amplitude and adjusts the selected first digital amplitude to reduce the selected second digital amplitude to lower than or equal to the full-scale digital amplitude. As such, it is possible to overcome digital amplitude clipping without increasing the predefined number of binary bits, thus achieving a calculated balance between performance, complexity, and cost.
9 Citations
28 Claims
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1. A gain level control circuit in a wireless communications system (WCS), comprising:
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a digital signal distribution circuit comprising a plurality of digital signal inputs and a plurality of digital signal outputs, the digital signal distribution circuit configured to; receive a plurality of first digital communications signals having a plurality of first digital amplitudes from the plurality of digital signal inputs, respectively; and generate a plurality of second digital communications signals having a plurality of second digital amplitudes at the plurality of digital signal outputs based on the plurality of first digital communications signals, wherein each of the plurality of second digital amplitudes is represented up to a full-scale digital amplitude in a predefined number of binary bits; and a digital signal processing circuit coupled to the plurality of digital signal inputs, the digital signal processing circuit configured to; determine that a selected second digital communications signal among the plurality of second digital communications signals has a selected second digital amplitude among the plurality of second digital amplitudes approaching the full-scale digital amplitude that can be represented by the predefined number of binary bits; determine a selected first digital communications signal among the plurality of first digital communications signals having a selected first digital amplitude causing the selected second digital amplitude to approach the full-scale digital amplitude; and control the digital signal distribution circuit to adjust the selected first digital amplitude to reduce the selected second digital amplitude. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for supporting dynamic gain control in a wireless communications system (WCS), comprising:
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receiving a plurality of first digital communications signals having a plurality of first digital amplitudes, respectively; generating a plurality of second digital communications signals having a plurality of second digital amplitudes based on the plurality of first digital communications signals, wherein each of the plurality of second digital amplitudes is represented up to a full-scale digital amplitude in a predefined number of binary bits; determining that a selected second digital communications signal among the plurality of second digital communications signals has a selected second digital amplitude among the plurality of second digital amplitudes approaching the full-scale digital amplitude that can be represented by the predefined number of binary bits; determining a selected first digital communications signal among the plurality of first digital communications signals having a selected first digital amplitude causing the selected second digital amplitude to approach the full-scale digital amplitude; and adjusting the selected first digital amplitude to reduce the selected second digital amplitude. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A head-end unit (HEU) in a wireless communications system (WCS) comprising a gain level control circuit, the gain level control circuit comprising:
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a digital signal distribution circuit comprising a plurality of digital signal inputs and a plurality of digital signal outputs, the digital signal distribution circuit configured to; receive a plurality of first digital communications signals having a plurality of first digital amplitudes from the plurality of digital signal inputs, respectively; and generate a plurality of second digital communications signals having a plurality of second digital amplitudes at the plurality of digital signal outputs based on the plurality of first digital communications signals, wherein each of the plurality of second digital amplitudes is represented up to a full-scale digital amplitude in a predefined number of binary bits; and a digital signal processing circuit coupled to the plurality of digital signal inputs, the digital signal processing circuit configured to; determine that a selected second digital communications signal among the plurality of second digital communications signals has a selected second digital amplitude among the plurality of second digital amplitudes approaching the full-scale digital amplitude that can be represented by the predefined number of binary bits; determine a selected first digital communications signal among the plurality of first digital communications signals having a selected first digital amplitude causing the selected second digital amplitude to approach the full-scale digital amplitude; and control the digital signal distribution circuit to adjust the selected first digital amplitude to reduce the selected second digital amplitude. - View Dependent Claims (21)
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22. A digital routing unit (DRU) in a wireless communications system (WCS) comprising a gain level control circuit, the gain level control circuit comprising:
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a digital signal distribution circuit comprising a plurality of digital signal inputs and a plurality of digital signal outputs, the digital signal distribution circuit configured to; receive a plurality of first digital communications signals having a plurality of first digital amplitudes from the plurality of digital signal inputs, respectively; and generate a plurality of second digital communications signals having a plurality of second digital amplitudes at the plurality of digital signal outputs based on the plurality of first digital communications signals, wherein each of the plurality of second digital amplitudes is represented up to a full-scale digital amplitude in a predefined number of binary bits; and a digital signal processing circuit coupled to the plurality of digital signal inputs, the digital signal processing circuit configured to; determine that a selected second digital communications signal among the plurality of second digital communications signals has a selected second digital amplitude among the plurality of second digital amplitudes approaching the full-scale digital amplitude that can be represented by the predefined number of binary bits; determine a selected first digital communications signal among the plurality of first digital communications signals having a selected first digital amplitude causing the selected second digital amplitude to approach the full-scale digital amplitude; and control the digital signal distribution circuit to adjust the selected first digital amplitude to reduce the selected second digital amplitude.
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23. A wireless distribution system (WDS), comprising:
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a plurality of remote units; and a head-end unit (HEU) coupled to the plurality of remote units via a plurality of communications mediums, respectively, the HEU configured to; distribute a plurality of downlink communications signals to the plurality of remote units via the plurality of communications mediums, respectively; and receive a plurality of uplink communications signals from the plurality of remote units via the plurality of communications mediums, respectively; wherein the HEU comprises a gain level control circuit, the gain level control circuit comprises; a digital signal distribution circuit comprising a plurality of digital signal inputs and a plurality of digital signal outputs, the digital signal distribution circuit configured to; receive a plurality of first digital communications signals having a plurality of first digital amplitudes from the plurality of digital signal inputs, respectively; and generate a plurality of second digital communications signals having a plurality of second digital amplitudes at the plurality of digital signal outputs based on the plurality of first digital communications signals, wherein each of the plurality of second digital amplitudes is represented up to a full-scale digital amplitude in a predefined number of binary bits; and a digital signal processing circuit coupled to the plurality of digital signal inputs, the digital signal processing circuit configured to; determine that a selected second digital communications signal among the plurality of second digital communications signals has a selected second digital amplitude among the plurality of second digital amplitudes approaching the full-scale digital amplitude that can be represented by the predefined number of binary bits; determine a selected first digital communications signal among the plurality of first digital communications signals having a selected first digital amplitude causing the selected second digital amplitude to approach the full-scale digital amplitude; and control the digital signal distribution circuit to adjust the selected first digital amplitude to reduce the selected second digital amplitude. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification