Downstream device service latency reporting for power management

• US 10,182,398 B2
• Filed: 03/08/2017
• Issued: 01/15/2019
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jeyaseelan, Jaya L., Walsh, Jim, Gough, Robert E., Cooper, Barnes, Songer, Neil W.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US15/453,208
• Publication Number:
  US 20170177539A1
• Time in Patent Office: 678 Days
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H04L 43/0858 One way delays
• CPC Class Codes: H04W 52/0225 using monitoring of external events, e.g. the presence of a signal
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.

Claims

1. A system comprising:

a processor;

a memory controller coupled to the processor to provide access to a system memory; and

an interface controller to communicate with an endpoint device, the interface controller coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device;

wherein the endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state; and

wherein the service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.

2. The system of claim 1, wherein the endpoint device is a peripheral component interconnect express (PCIe) endpoint device.

3. The system of claim 1, further comprising a communication interface to communicate over a network.

4. The system of claim 1, further comprising a graphics controller.