Near-memory compute module

• US 10,185,499 B1
• Filed: 11/07/2014
• Issued: 01/22/2019
• Est. Priority Date: 01/07/2014
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Wang, David, Saxena, Nirmal
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Puche, Tahilba O
• Application Number:
  US14/536,312
• Time in Patent Office: 1,537 Days
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

Claims

1. An integrated circuit device disposed within an integrated circuit package having a periphery, the integrated circuit device within the periphery comprising:

a transaction processor; and

one or more memory controllers coupled to the transaction processor, the one or more memory controllers to execute one or more memory access operations, wherein a plurality of DRAM devices is coupled to the one or more memory controllers, the plurality of DRAM devices to respond to the one or more memory access operations, wherein the transaction processor is to;

receive a combination of signals from a host controller;

intercept a first portion of the combination of signals;

decode a command in the first portion;

determine, based on the command, a set of one or more instructions to perform a data transformation of data in a memory by the transaction processor;

execute the set of instructions to perform the data transformation during one or more wait times after the first portion of the combination of signals is intercepted and before operation results from the data transformation are expected by the host controller;

determine operation results from the set of instructions;

decode a second portion of the combination of signals;

forward the second portion of the combination of signals to be used by the one or more memory controllers to initiate execution of a write access operation or a read access operation of the one or more memory access operations; and

when the second portion corresponds to the write access operation, receive write data associated with the write access operation from the host controller and forward the write data to the one or more memory controllers; and

when the second portion corresponds to the read access operation, receive read data associated with the read access operation from the one or more memory controllers and forward the read data during one or more wait times after the first portion of the combination of signals is intercepted and before operation results from the data transformation are expected by the host controller to the host controller,

wherein the transaction processor comprises a set of data buffers to drive and receive the combination of signals and allow the plurality of DRAM devices to emulate a type of Dual In-Line Memory Module (DIMM) selected from an un-buffered DIMM type (UDIMM), a load-reduction DIMM type (LRDIMM), and a registered DIMM type (RDIMM).

2. The integrated circuit device of claim 1, wherein the transaction processor is to communicate with a host controller using a physical interface so as to appear as a physical memory, wherein the physical memory comprises one or more of the plurality of DRAM devices.

3. The integrated circuit device of claim 1, further comprising the plurality of DRAM devices.

4. The integrated circuit device of claim 3, wherein the transaction processor is to communicate with a host controller using a physical interface so as to appear as a physical memory, the physical memory being one or more of the plurality of DRAM devices.

5. The integrated circuit device of claim 1, wherein the transaction processor comprises a control plane to decode one or more commands from the first portion.

6. The integrated circuit device of claim 5, wherein the transaction processor comprises a data plane to store a software driver payload and accept the commands from the control plane to execute the data transformation.

7. The integrated circuit device of claim 6, wherein the control plane and the data plane are implemented with Static Random Access Memory (SRAM).

8. The integrated circuit device of claim 1, further comprising one or more off-load engines coupled to the transaction processor, wherein the transaction processor is to launch a data transformation operation on the off-load engines to perform the data transformation.

9. The integrated circuit device of claim 8, further comprising one or more processor cores coupled to the one or more off-load engines, wherein the transaction processor is to use the one or more processor cores and the one or more processor cores to accelerate the execution of the data transformation.

10. A near memory computing system comprising:

a transaction processor;

a plurality of dynamic random access memory (DRAM) devices; and

at least one memory controller coupled to the transaction processor and the plurality of DRAM devices, the memory controller to perform one or more memory access operations over at least some of the plurality of DRAM devices, the memory controller further to perform an error detection and correction process by storing an error condition to accumulate a history of a plurality of error occurrences and initiating a memory repair process based on the history;

wherein the transaction processor is to receive a combination of signals from the at least one memory controller, and wherein the transaction processor intercepts a first portion of the combination of signals, decode a command in the first portion;

determine, based on the command, a set of one or more instructions to perform a data transformation of data in a memory by the transaction processor, execute the set of instructions to perform the data transformation during one or more wait times after the first portion of the combination of signals is intercepted and before operation results from the data transformation are expected by the at least one memory controller, determine operation results from the set of instructions, decode a second portion of the combination of signals, and forward the second portion of the combination of signals to initiate execution of a write access operation or a read access operation of the one or more memory access operations, wherein;

when the second portion corresponds to the write access operation, the transaction processor is to receive write data associated with the write access operation from the at least one memory controller and forward the write data to the plurality of DRAM devices; and

when the second portion corresponds to the read access operation, the transaction processor is receive read data associated with the read access operation from the plurality of DRAM devices and forward the read data and the operation results to the at least one memory controller.

11. The system of claim 10, wherein the transaction processor is to communicate with a host controller using a physical interface so as to appear as a physical memory, the physical memory being one or more of the plurality of DRAM devices.

12. The system of claim 10, wherein the transaction processor comprises a control plane to decode one or more commands from the first portion.

13. The system of claim 12, wherein the transaction processor comprises a data plane to store a software driver payload and accept the commands from the control plane to execute the data transformation.

14. The system of claim 10, wherein the transaction processor comprises a set of data buffers to drive and receive the combination of signals.

15. The system of claim 10, further comprising one or more off-load engines coupled to the transaction processor, wherein the transaction processor is to launch a data transformation operation on the one or more off-load engines to perform the data transformation.

16. The system of claim 15, further comprising one or more processor cores coupled to the one or more off-load engines and configured to accelerate the execution of the data transformation.

17. The system of claim 10, further comprising one or more flash controllers coupled to one or more flash memory devices.

18. The system of claim 10, further comprising one or more off-load engines coupled to the transaction processor, the off-load engines to perform the data transformation.

19. The system of claim 18, further comprising one or more processor cores coupled to the one or more off-load engines, wherein the transaction processor is to use the one or more processor cores and the one or more processor cores to accelerate the execution of the data transformation.