Transaction begin/end instructions

• US 10,185,588 B2
• Filed: 05/23/2016
• Issued: 01/22/2019
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Greiner, Dan F., Jacobi, Christian, Mitran, Marcel, Slegel, Timothy J.
• Primary Examiner(s): Pham, Tuan A
• Application Number:
  US15/161,900
• Publication Number:
  US 20160266927A1
• Time in Patent Office: 974 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.

Claims

1. A computer program product for executing a machine instruction in a computing environment, said computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

obtaining a machine instruction for operation, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

an operation code to specify a transaction begin operation;

one or more fields to specify a first operand address; and

a control field, the control field comprising a general register save mask to indicate one or more pairs of registers to be saved at a beginning of a transaction and restored on an abort; and

executing the machine instruction, the executing comprising;

determining, using a field of the machine instruction, whether the transaction to be initiated by the machine instruction is a constrained transaction or a nonconstrained transaction;

based on the field being one value, initiating a constrained transaction, the constrained transaction having two or more restrictions associated therewith, and setting a condition code to indicate successful execution of the machine instruction, the two or more restrictions including restrictions selected from the group consisting of;

a subset of general instructions is available, a limited number of instructions is to be executed, a limited number of storage-operand locations is to be accessed, and the constrained transaction is limited to a single nesting level; and

based on the field being another value;

initiating a nonconstrained transaction;

using the first operand address to designate a location of a transaction diagnostic block to store diagnostic information based on the nonconstrained transaction being aborted; and

setting a condition code to indicate successful execution of the machine instruction.

2. The computer program product of claim 1, wherein the field comprises the operation code.

3. The computer program product of claim 1, wherein the field indicates a nonconstrained transaction, and wherein the control field further comprises:

an allow access register modification field to control whether the transaction is allowed to modify an access register;

an allow floating point operation field to control whether the transaction is allowed to execute specified floating point instructions; and

a program interruption filtering control field to control whether certain classes of program interruption conditions result in an interruption.

4. The computer program product of claim 1, wherein the control field further comprises an allow access register modification field to control whether the transaction is allowed to modify an access register.

5. The computer program product of claim 1, wherein the machine instruction further comprises a base field, and wherein based on the base field comprising one value, contents of a register specified by the base field are combined with contents of a displacement field to create the first operand address.

6. The computer program product of claim 1, wherein the two or more restrictions comprise:

a limited number of instructions within the transaction;

instructions within the transaction are to be within a pre-defined area of memory;

certain pre-specified instructions can be included within the transaction, others are restricted;

a limit on access by storage operands of the transaction;

the transaction does not access storage operands in blocks of memory that contain the pre-defined area of memory;

the transaction does not access instructions or storage operands using different logical addresses mapped to a same absolute address; and

operand references made by the transaction are to be within a specified size.

7. The computer program product of claim 1, wherein the method further comprises:

executing another machine instruction to end the transaction initiated by the transaction begin instruction, the other machine instruction comprising a transaction end instruction, the transaction end instruction comprising an operation code to indicate the transaction end instruction.

8. The computer program product of claim 7, wherein the executing the other machine instruction comprises:

decrementing a transactional nesting depth;

determining whether the decremented transactional nesting depth is zero; and

committing store accesses made by the transaction based on the decremented transactional nesting depth being zero.

9. A computer system for executing a machine instruction in a computing environment, said computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising;

obtaining a machine instruction for operation, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

an operation code to specify a transaction begin operation;

one or more fields to specify a first operand address; and

a control field, the control field comprising a general register save mask to indicate one or more pairs of registers to be saved at a beginning of a transaction and restored on an abort; and

executing the machine instruction, the executing comprising;

determining, using a field of the machine instruction, whether the transaction to be initiated by the machine instruction is a constrained transaction or a nonconstrained transaction;

based on the field being one value, initiating a constrained transaction, the constrained transaction having two or more restrictions associated therewith, and setting a condition code to indicate successful execution of the machine instruction, the two or more restrictions including restrictions selected from the group consisting of;

a subset of general instructions is available, a limited number of instructions is to be executed, a limited number of storage-operand locations is to be accessed, and the constrained transaction is limited to a single nesting level; and

based on the field being another value;

initiating a nonconstrained transaction;

using the first operand address to designate a location of a transaction diagnostic block to store diagnostic information based on the nonconstrained transaction being aborted; and

setting a condition code to indicate successful execution of the machine instruction.

10. The computer system of claim 9, wherein the field indicates a nonconstrained transaction, and wherein the control field further comprises:

an allow access register modification field to control whether the transaction is allowed to modify an access register;

an allow floating point operation field to control whether the transaction is allowed to execute specified floating point instructions; and

a program interruption filtering control field to control whether certain classes of program interruption conditions result in an interruption.

11. The computer system of claim 9, wherein the control field further comprises an allow access register modification field to control whether the transaction is allowed to modify an access register.

12. The computer system of claim 9, wherein the two or more restrictions comprise:

a limited number of instructions within the transaction;

instructions within the transaction are to be within a pre-defined area of memory;

certain pre-specified instructions can be included within the transaction, others are restricted;

a limit on access by storage operands of the transaction;

the transaction does not access storage operands in blocks of memory that contain the pre-defined area of memory;

the transaction does not access instructions or storage operands using different logical addresses mapped to a same absolute address; and

operand references made by the transaction are to be within a specified size.

13. The computer system of claim 9, wherein the method further comprises:

executing another machine instruction to end the transaction initiated by the transaction begin instruction, the other machine instruction comprising a transaction end instruction, the transaction end instruction comprising an operation code to indicate the transaction end instruction, and wherein the executing the other machine instruction comprises;

decrementing a transactional nesting depth;

determining whether the decremented transactional nesting depth is zero; and

committing store accesses made by the transaction based on the decremented transactional nesting depth being zero.

14. The computer system of claim 9, wherein the machine instruction further comprises a base field, and wherein based on the base field comprising one value, contents of a register specified by the base field are combined with contents of a displacement field to create the first operand address.

15. A computer-implemented method of executing a machine instruction in a computing environment, said computer-implemented method comprising:

obtaining, by a processor, a machine instruction for operation, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

an operation code to specify a transaction begin operation;

one or more fields to specify a first operand address; and

a control field, the control field comprising a general register save mask to indicate one or more pairs of registers to be saved at a beginning of a transaction and restored on an abort; and

executing the machine instruction, the executing comprising;

determining, using a field of the machine instruction, whether the transaction to be initiated by the machine instruction is a constrained transaction or a nonconstrained transaction;

based on the field being one value, initiating a constrained transaction, the constrained transaction having two or more restrictions associated therewith, and setting a condition code to indicate successful execution of the machine instruction, the two or more restrictions including restrictions selected from the group consisting of;

a subset of general instructions is available, a limited number of instructions is to be executed, a limited number of storage-operand locations is to be accessed, and the constrained transaction is limited to a single nesting level; and

based on the field being another value;

initiating a nonconstrained transaction;

using the first operand address to designate a location of a transaction diagnostic block to store diagnostic information based on the nonconstrained transaction being aborted; and

setting a condition code to indicate successful execution of the machine instruction.

16. The computer-implemented method of claim 15, wherein the field indicates a nonconstrained transaction, and wherein the control field further comprises:

an allow access register modification field to control whether the transaction is allowed to modify an access register;

an allow floating point operation field to control whether the transaction is allowed to execute specified floating point instructions; and

a program interruption filtering control field to control whether certain classes of program interruption conditions result in an interruption.

17. The computer-implemented method of claim 15, wherein the control field further comprises an allow access register modification field to control whether the transaction is allowed to modify an access register.

18. The computer-implemented method of claim 15, wherein the two or more restrictions comprise:

a limited number of instructions within the transaction;

instructions within the transaction are to be within a pre-defined area of memory;

certain pre-specified instructions can be included within the transaction, others are restricted;

a limit on access by storage operands of the transaction;

the transaction does not access storage operands in blocks of memory that contain the pre-defined area of memory;

the transaction does not access instructions or storage operands using different logical addresses mapped to a same absolute address; and

operand references made by the transaction are to be within a specified size.

19. The computer-implemented method of claim 15, further comprising:

executing another machine instruction to end the transaction initiated by the transaction begin instruction, the other machine instruction comprising a transaction end instruction, the transaction end instruction comprising an operation code to indicate the transaction end instruction, and wherein the executing the other machine instruction comprises;

decrementing a transactional nesting depth;

determining whether the decremented transactional nesting depth is zero; and

committing store accesses made by the transaction based on the decremented transactional nesting depth being zero.

20. The computer-implemented method of claim 15, wherein the machine instruction further comprises a base field, and wherein based on the base field comprising one value, contents of a register specified by the base field are combined with contents of a displacement field to create the first operand address.