Handling of error prone cache line slots of memory side cache of multi-level system memory

• US 10,185,619 B2
• Filed: 03/31/2016
• Issued: 01/22/2019
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yigzaw, Theodros, Raj, Ashok, Swanson, Robert, Kumar, Mohan J.
• Primary Examiner(s): Ko, Chae M
• Application Number:
  US15/087,797
• Publication Number:
  US 20170286210A1
• Time in Patent Office: 1,027 Days
• Field of Search: 714 611
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/22 Employing cache memory using specific memory technology
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

Claims

1. An apparatus, comprising:

memory controller logic circuitry to interface with a memory side cache of a multi-level system memory, said memory controller logic circuitry comprising error tracking circuitry to track errors of cache line slots in said memory side cache, said memory controller logic circuitry also comprising faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone, said memory controller logic circuitry to declare a miss in said memory side cache for requests that map to cache line slots identified in said faulty list, said memory controller further comprising a local cache to identify cache lines kept in said memory side cache, wherein, said memory controller logic circuitry is to fetch a cache line from said memory side cache if it is identified in said local cache and its corresponding cache line slot is not identified on said faulty list.

2. The apparatus of claim 1 wherein said identifiers comprise addresses of faulty cache line slots.

3. The apparatus of claim 1 wherein said memory controller logic circuitry is further to write back a cache line resident in a faulty cache line slot to a far memory of the multi-level system memory if the resident cache line is dirty.

4. The apparatus of claim 1 wherein said memory controller logic circuitry is to prevent read data of a read request from being written into said memory side cache for a cache line that maps to faulty cache line slot and that was serviced from a far memory of the multi-level system memory that said memory side cache is a cache for.

5. The apparatus of claim 1 wherein said memory controller logic circuitry is further to not perform a read of a cache line from said memory side cache if its corresponding cache line slot is identified on said faulty list.

6. A computing system, comprising:

a plurality of processing cores;

a display;

a multi-level system memory;

memory controller logic circuitry to interface with a memory side cache of said multi-level system memory, said memory controller logic circuitry comprising error tracking circuitry to track errors of cache line slots in said memory side cache, said memory controller logic circuitry also comprising faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone, said memory controller logic circuitry to declare a miss in said memory side cache for requests that map to cache line slots identified in said faulty list, said memory controller further comprising a local cache to identify cache lines kept in said memory side cache, wherein, said memory controller logic circuitry is to fetch a cache line from said memory side cache if it is identified in said local cache and its corresponding cache line slot is not identified on said faulty list.

7. The computing system of claim 6 wherein said identifiers comprise addresses of faulty cache line slots.

8. The computing system of claim 6 wherein said memory controller logic circuitry is further to write back a cache line resident in a faulty cache line slot to a far memory of the multi-level system memory if the resident cache line is dirty.

9. The computing system of claim 6 wherein said memory controller logic circuitry is to prevent read data of a read request from being written into said memory side cache for a cache line that maps to faulty line slot and that was serviced from a far memory of the multi-level system memory that said memory side cache is a cache for.

10. The computing system of claim 6 wherein said memory controller logic circuitry is further to not perform a read of a cache line from said memory side cache if its corresponding cache line slot is identified on said faulty list.

11. A method, comprising:

tracking errors of cache line slots of a memory side cache of a multi-level system memory;

identifying a cache line slot that demonstrates excessive errors;

identifying said cache line slot on a faulty list;

receiving a request for a cache line that maps to said cache line slot;

recognizing that said cache line slot is identified on said faulty list and declaring a miss in said memory side cache for said request in response;

identifying cache lines kept in said memory side cache in a local cache;

fetching a cache line from said memory side cache if it is identified in said local cache and its corresponding cache line slot is not identified on said faulty list.

12. The method of claim 11 wherein said cache line slot is identified on said list by its address.

13. The method of claim 11 further comprising re-directing said request to a far memory of the multi-level system memory that said memory side cache acts as a cache for.

14. The method of claim 11 further comprising writing said cache line back to a far memory of the multi-level system memory that said memory side cache acts as a cache for because said cache line is resident in said memory side cache and is dirty.