Methods for reprogramming data and apparatuses using the same

• US 10,185,662 B2
• Filed: 07/24/2017
• Issued: 01/22/2019
• Est. Priority Date: 03/04/2015
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Hsu, Che-Wei
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US15/657,697
• Publication Number:
  US 20170322880A1
• Time in Patent Office: 547 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A method for reprogramming data, performed by a processing unit, is disclosed to include at least the following steps. When a page data has failed to be programmed into a first block of a storage unit and the failed page is an upper page of the first block, a host page number associated with a first lower page of memory cells of the first block of a wordline is obtained, where the memory cells comprises the failed page. When the failed page is an upper page, data from the first lower page to the upper page of the first block is programmed into a second block of the storage unit.

Claims

1. A method for reprogramming data, performed by a processing unit, comprising:

when a page of data has failed to be programmed into a first block of a storage unit and the failed page is an upper page of the first block, obtaining, by the processing unit, a host page number associated with a first lower page of the first block corresponding to a wordline from the storage unit, wherein the first block comprises the upper page, the first lower page and at least one intermediate page which is between the first lower page and the upper page, and the first lower page, the intermediate page and the upper page are associated with consecutive host page numbers; and

when the failed page is the upper page of the first block, reprograming, by the processing unit, data from the first lower page to the upper page of the first block into a second block of the storage unit.

2. The method of claim 1, wherein the wordline corresponds to a plurality of memory cells, each memory cell stores information of a LSB (Least Significant Bit) and a MSB (Most Significant Bit), the LSBs of the memory cells collectively form the first lower page of the first block and the MSBs of the memory cells collectively form the upper page of the first block.

3. The method of claim 1, further comprising:

when the failed page is the upper page of the first block, reading, by the processing unit, data associated with the consecutive host page numbers from a DRAM (Dynamic Random Access Memory) and storing the read data in a data buffer; and

when the failed page is the upper page of the first block, reprograming, by the processing unit, the data of the data buffer into the second block.

4. The method of claim 1, further comprising:

when the failed page is a second lower page of the first block, reprograming, by the processing unit, data of the first lower page into the second block.

5. The method of claim 1, further comprising:

filling, by the processing unit, unused pages of the first block with dummy values.

6. The method of claim 1, further comprising:

determining, by the processing unit, whether the page of data has failed to be programmed into the first block of the storage unit.

7. The method of claim 6, wherein the step for determining whether the page of data has failed to be programmed into the first block of the storage unit comprises:

inspecting, by the processing unit, a register through an access interface to determine whether the page of data has failed to be programmed into the first block of the storage unit, wherein the register is set by control circuits to notify the processing unit an execution outcome associated with a programming of the page of data.

8. The method of claim 1, further comprising:

setting, by the processing unit, a physical storage location associated with the host page number, which is stored in a storage mapping table, to point to the second block.

9. An apparatus for reprogramming data, comprising:

an access interface, coupled to a storage unit; and

a processing unit, coupled to the access interface, after inspecting that a page of data has failed to be programmed into a first block of the storage unit and the failed page is an upper page of the first block, obtaining a host page number associated with a first lower page of the first block corresponding to a wordline from the storage unit, and directing the access interface to reprogram data from the first lower page to the upper page of the first block into a second block of the storage unit, wherein the first block comprises the upper page, the first lower page and at least one intermediate page which is between the first lower page and the upper page, and the first lower page, the intermediate page and the upper page are associated with consecutive host page numbers.

10. The apparatus of claim 9, wherein the wordline corresponds to a plurality of memory cells, each memory cell stores information of a LSB (Least Significant Bit) and a MSB (Most Significant Bit), the LSBs of the memory cells collectively form the first lower page of the first block and the MSBs of the memory cells collectively form the upper page of the first block.

11. The apparatus of claim 9, wherein when the failed page is the upper page of the first block, the processing unit reads data associated with the consecutive host page numbers from a DRAM (Dynamic Random Access Memory), stores the read data in a data buffer and directs the access interface to reprogram the data of the data buffer into the second block.

12. The apparatus of claim 9, wherein when the failed page is a second lower page of the first block, the processing unit directs the access interface to reprogram data of the second lower page into the second block.

13. The apparatus of claim 9, wherein the processing unit further fills unused pages of the first block with dummy values.

14. The apparatus of claim 9, wherein the processing unit further determines whether the page of data has failed to be programmed into the first block of the storage unit by inspecting a register, wherein the register is set by control circuits to notify the processing unit an execution outcome associated with a programming of the page of data.

15. The apparatus of claim 14, wherein the processing unit inspects a register setting through the access interface to determine whether the page of data has failed to be programmed into the first block of the storage unit.

16. The apparatus of claim 9, wherein the processing unit further sets a physical storage location associated with the host page number, which is stored in a storage mapping table, to point to the second block.