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Reconfigurable data interface unit for compute systems

  • US 10,185,699 B2
  • Filed: 03/14/2016
  • Issued: 01/22/2019
  • Est. Priority Date: 03/14/2016
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a first set of line buffers configured to receive and store, for a first data cycle, a plurality of data blocks from a memory of a system-on-chip (SoC) via at least one data bus, wherein each data block has a first data structure and a first bit width;

    a field composition circuit configured to generate a plurality of data segments from each of the data blocks according to a plurality of reconfiguration schemes, the generating including decomposing each data block of the plurality from the first set of line buffers into the plurality of data segments, and each data segment has a second bit width that is less than the first bit width;

    a second set of line buffers configured to communicate with the field composition circuit to store, for a second data cycle following the first data cycle, the plurality of data segments for each data block;

    a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the SoC;

    a set of input/output (I/O) buffers configured to store, for a third data cycle following the second data cycle, the plurality of data streams;

    a set of streaming buffers storing data of a first processing unit based on selectively reading from each I/O buffer; and

    a reconfigurable data interface (RDIU) receiving the plurality of data blocks from a plurality of data buses.

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