Reconfigurable data interface unit for compute systems
First Claim
1. An apparatus, comprising:
- a first set of line buffers configured to receive and store, for a first data cycle, a plurality of data blocks from a memory of a system-on-chip (SoC) via at least one data bus, wherein each data block has a first data structure and a first bit width;
a field composition circuit configured to generate a plurality of data segments from each of the data blocks according to a plurality of reconfiguration schemes, the generating including decomposing each data block of the plurality from the first set of line buffers into the plurality of data segments, and each data segment has a second bit width that is less than the first bit width;
a second set of line buffers configured to communicate with the field composition circuit to store, for a second data cycle following the first data cycle, the plurality of data segments for each data block;
a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the SoC;
a set of input/output (I/O) buffers configured to store, for a third data cycle following the second data cycle, the plurality of data streams;
a set of streaming buffers storing data of a first processing unit based on selectively reading from each I/O buffer; and
a reconfigurable data interface (RDIU) receiving the plurality of data blocks from a plurality of data buses.
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Accused Products
Abstract
A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.
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Citations
21 Claims
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1. An apparatus, comprising:
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a first set of line buffers configured to receive and store, for a first data cycle, a plurality of data blocks from a memory of a system-on-chip (SoC) via at least one data bus, wherein each data block has a first data structure and a first bit width; a field composition circuit configured to generate a plurality of data segments from each of the data blocks according to a plurality of reconfiguration schemes, the generating including decomposing each data block of the plurality from the first set of line buffers into the plurality of data segments, and each data segment has a second bit width that is less than the first bit width; a second set of line buffers configured to communicate with the field composition circuit to store, for a second data cycle following the first data cycle, the plurality of data segments for each data block; a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the SoC; a set of input/output (I/O) buffers configured to store, for a third data cycle following the second data cycle, the plurality of data streams; a set of streaming buffers storing data of a first processing unit based on selectively reading from each I/O buffer; and a reconfigurable data interface (RDIU) receiving the plurality of data blocks from a plurality of data buses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of data processing by a system-on-chip, comprising:
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storing a plurality of data blocks in a first set of line buffers for a first data cycle, wherein each data block has a first data structure and a first bit width; generating from each of the plurality of data blocks a plurality of data segments, the generating including decomposing each data block of the plurality from the first set of line buffers into the plurality of data segments, and each data segment has a second bit width that is less than the first bit width; storing the plurality of data segments for each data block in a second set of line buffers for a second data cycle following the first data cycle; selectively reading from the second set of line buffers to combine portions of data segments from multiple data blocks to form a plurality of data streams; storing the plurality of data streams in a set of input/output (I/O) buffers for a third data cycle following the second data cycle and based on a plurality of execution patterns for a processing unit of a system-on-chip (SoC); storing data in a set of streaming buffers of a first processing unit based on selectively reading from each I/O buffer; and receiving at a reconfigurable data interface unit (RDIU) the plurality of data blocks from a plurality of data buses. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A system-on-chip, comprising:
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one or more non-transitory memory devices comprising instructions; a plurality of buses coupled to the one or more memory devices; a plurality of compute systems coupled to the plurality of buses, each compute system comprising one or more processing units to execute the instructions to; store a plurality of data blocks in a first set of line buffers for a first data cycle, wherein each data block has a first data structure and a first bit width; generate from each of the plurality of data blocks a plurality of data segments, the generating including decomposing each data block of the plurality from the first set of line buffers into the plurality of data segments, and each data segment has a second bit width that is less than the first bit width; store the plurality of data segments for each data block in a second set of line buffers for a second data cycle following the first data cycle; selectively read from the second set of line buffers to combine portions of data segments from multiple data blocks to form a plurality of data streams; store the plurality of data streams in a set of input/output (I/O) buffers for a third data cycle following the second data cycle and based on a plurality of execution patterns for a processing unit of a system-on-chip (SoC); store data in a set of streaming buffers of a first processing unit based on selectively reading from each I/O buffer; and receive at a reconfigurable data interface unit (RDIU) the plurality of data blocks from a plurality of data buses. - View Dependent Claims (18, 19, 20, 21)
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Specification