Display system

• US 10,186,231 B2
• Filed: 01/06/2017
• Issued: 01/22/2019
• Est. Priority Date: 06/16/2016
• Status: Active Grant

• Current Assignee: Forcelead Technology Corp.
• Original Assignee: Sitronix Technology Corporation
• Inventors: Chang, Chih-Wei, Peng, Shih-Wei
• Primary Examiner(s): Haley, Joseph R
• Application Number:
  US15/400,128
• Publication Number:
  US 20170365232A1
• Time in Patent Office: 746 Days
• Field of Search: None
• CPC Class Codes: B60Y 2400/92 Driver displays
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 2380/10 Automotive applications
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

This disclosure provides a display system, which comprises: a mainframe; a control module comprising an image processing unit and an image compositing unit, communicating with the mainframe through a first channel and a second channel, and generating an image signal; and a display panel showing pictures according to the image signal; wherein the mainframe provides the image processing unit with image data, parameter data and control signals through both the first and second channels when the first channel works, and the image processing unit processes the image data and the parameter data and generates a first data signal to be the image signal; wherein the mainframe provides the image compositing unit with response data through the second channel when the first channel fails, and the image compositing unit combines the response data and a pre-determined background into a second data signal to be the image signal.

Claims

1. A display system comprising:

a mainframe;

a control circuit comprising an image processing unit and an image compositing circuit, communicating with the mainframe through a first channel and a second channel, and generating an image signal; and

a display panel showing pictures according to the image signal;

wherein the mainframe provides the image processing unit with image data, parameter data and control signals through both the first and second channels when the first channel works, and the image processing unit processes the image data and the parameter data and generates a first data signal to be the image signal;

wherein the mainframe provides the image compositing circuit with response data through the second channel when the first channel fails, and the image compositing circuit combines the response data and a pre-determined background into a second data signal to be the image signal;

wherein the response data include at least one of a numerical digit and a status flag, or the pre-determined background includes at least one indicator of vehicle speed, motor rotation rate, engine coolant temperature and fuel level.

2. The display system of claim 1, wherein the first and second channels share a single physical circuit.

3. The display system of claim 1, wherein the first and second channels use different physical circuits.

4. The display system of claim 1, wherein the control circuit further includes:

a multiplexer selecting one of the first and second data signals as the image signal generated by the control circuit, according to either a command signal from the mainframe or a decision signal from the image processing unit.

5. The display system of claim 1, wherein the control signals include a clock signal, and the image processing unit judges whether the first channel works or fails by the clock signal'"'"'s frequency.

6. The display system of claim 5, wherein the control signals further include an enabling signal having two states of logic high and low levels, and the image processing unit judges whether the first channel works or fails by both the clock signal'"'"'s cycle period and the enabling signal'"'"'s duration at the logic high level.

7. The display system of claim 5, wherein the control signals further include a horizontal synchronization signal having two states of logic high and low levels, and the image processing unit judges whether the first channel works or fails by both the clock signal'"'"'s cycle period and the horizontal synchronization signal'"'"'s cycle period.

8. A display system comprising:

a mainframe;

a control circuit comprising an image processing unit and an image compositing circuit, communicating with the mainframe through a first channel and a second channel, and generating an image signal; and

a display panel showing pictures according to the image signal;

wherein the mainframe provides the image processing unit with image data, parameter data and control signals through both the first and second channels when the first channel works, and the image processing unit processes the image data and the parameter data and generates a first data signal to be the image signal;

wherein the mainframe provides the image compositing circuit with response data through the second channel when the first channel fails, and the image compositing circuit combines the response data and a pre-determined background into a second data signal to be the image signal;

wherein the control signals include a clock signal and an enabling signal having two states of logic high and low levels, and the image processing unit judges whether the first channel works or fails by the clock signal'"'"'s frequency, the clock signal'"'"'s cycle period and the enabling signal'"'"'s duration at the logic high level.

9. The display system of claim 8, wherein the first and second channels share a single physical circuit.

10. The display system of claim 8, wherein the first and second channels use different physical circuits.

11. The display system of claim 8, wherein the control circuit further includes:

a multiplexer selecting one of the first and second data signals as the image signal generated by the control circuit, according to either a command signal from the mainframe or a decision signal from the image processing unit.

12. A display system comprising:

a mainframe;

a control circuit comprising an image processing unit and an image compositing unit, communicating with the mainframe through a first channel and a second channel, and generating an image signal; and

a display panel showing pictures according to the image signal;

wherein the mainframe provides the image processing unit with image data, parameter data and control signals through both the first and second channels when the first channel works, and the image processing unit processes the image data and the parameter data and generates a first data signal to be the image signal;

wherein the mainframe provides the image compositing circuit with response data through the second channel when the first channel fails, and the image compositing circuit combines the response data and a pre-determined background into a second data signal to be the image signal;

wherein the control signals include a clock signal and a horizontal synchronization signal having two states of logic high and low levels, and the image processing unit judges whether the first channel works or fails by the clock signal'"'"'s frequency, the clock signal'"'"'s cycle period and the horizontal synchronization signal'"'"'s cycle period.

13. The display system of claim 12, wherein the first and second channels share a single physical circuit.

14. The display system of claim 12, wherein the first and second channels use different physical circuits.

15. The display system of claim 12, wherein the control circuit further includes:

a multiplexer selecting one of the first and second data signals as the image signal generated by the control circuit, according to either a command signal from the mainframe or a decision signal from the image processing unit.