Error correction for storage devices

• US 10,186,296 B2
• Filed: 03/14/2018
• Issued: 01/22/2019
• Est. Priority Date: 09/15/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Burd, Gregory, Varnica, Nedeljko, Tang, Heng
• Primary Examiner(s): Neyzari, Ali
• Application Number:
  US15/921,610
• Publication Number:
  US 20180204594A1
• Time in Patent Office: 314 Days
• Field of Search: 360 46
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11B 20/1217 on discs
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 2020/1222 ECC block, i.e. a block of error correction encoded symbols which includes all parity data needed for decoding
• CPC Class Codes: G11B 2020/1238 track, i.e. the entire a spirally or concentrically arranged path on which the recording marks are located

Abstract

A method for redundantly storing data includes receiving data at a storage controller, partitioning the data into a plurality of data blocks, generating a first error correction code associated with a first page within the plurality of data blocks, and generating a first redundancy code associated with at least two data blocks within the plurality of data block. The first redundancy code provides additional error recovery if the first error correction code fail. The method further includes storing the plurality of data blocks, the first error correction code, and the first redundancy code across a plurality of solid state storage devices.

Claims

1. A method for redundantly storing data, the method comprising:

receiving data at a storage controller;

partitioning the data into a plurality of data blocks;

generating a first error correction code associated with a first page within the plurality of data blocks;

generating a first redundancy code associated with at least two data blocks within the plurality of data blocks, wherein the first redundancy code provides additional error recovery if the first error correction code fails; and

storing the plurality of data blocks, the first error correction code, and the first redundancy code across a plurality of solid state storage devices.

2. The method of claim 1, wherein the first error correction code comprises parity information generated from the first page.

3. The method of claim 2, wherein the parity information is implemented within a hard decode error correction procedure.

4. The method of claim 2, wherein the parity information is implemented within a soft decode error correction procedure.

5. The method of claim 1, wherein the first redundancy code is generated using at least an XOR operation applied to the at least two data blocks.

6. The method of claim 1, wherein the first redundancy code is associated with a RAID-based error recovery operation.

7. The method of claim 1, wherein the plurality of solid state storage devices comprises at least two flash memory chips.

8. The method of claim 7, wherein the at least two flash memory chips implement multi-level cell storage.

9. The method of claim 7, wherein the at least two flash memory chips implement three-layer cell storage.

10. A method for recovering stored data, the method comprising:

receiving a request to read data stored within a plurality of solid state storage devices;

identifying a portion of data within the data, the portion of data having at least one error;

applying a first error recovery operation in an attempt to generate a first recovered data portion, the first error recovery operation implements a first error correction code;

applying a second error recovery operation if the first error recovery operation fails, the second error recovery operation implements a first redundancy code to generate a second recovered data portion; and

reading the data from the plurality of solid state storage devices, the data comprising at least one of the first recovered data portion and the second recovered data portion.

11. The method of claim 10, wherein the first error correction code comprises parity information.

12. The method of claim 11, wherein the first error recovery operation comprises at least one of a hard decode procedure using the parity information and a soft decode procedure using the parity information.

13. The method of claim 10, wherein the first redundancy code is generated using an XOR operation on at least two blocks within the data.

14. The method of claim 10, wherein the first redundancy code is associated with a RAID-based error recovery operation.

15. The method of claim 10, wherein the plurality of solid state storage devices comprises at least two flash memory chips.

16. A controller for storing data with redundancy, the controller comprising:

a processor coupled to receive a request to read data stored across a plurality of solid state storage devices;

an error-correcting code module coupled to the processor, wherein the error-correcting code module applies a first error recovery operation to at least one data portion having an error and the first error recovery operation implements a first error correction code in an attempt to recover the at least one data portion; and

a redundant array of independent blocks encoder coupled to the processor, wherein the redundant array of independent blocks encoder applies a second error recovery operation if the first error recovery operation fails and the second error recovery operation implements a first redundancy code to recover the at least one data portion.

17. The controller of claim 16, further comprising a redundancy check module that identifies errors within the data.

18. The controller of claim 16, further comprising at least one parity buffer coupled to the processor, wherein the at least one parity buffer stores at least one of the first error correction code and the first redundancy code.

19. The controller of claim 16, wherein the first error correction code includes parity information and the parity information is implemented within a soft decode error correction procedure.

20. The controller of claim 16, wherein the first redundancy code is generated using at least an XOR operation applied to at least two data blocks within the data.

21. The controller of claim 16, wherein the plurality of solid state storage devices comprises at least two flash memory chips.