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Semiconductor memory device

  • US 10,186,319 B2
  • Filed: 03/26/2018
  • Issued: 01/22/2019
  • Est. Priority Date: 09/06/2012
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, comprising:

  • a memory block includinga first memory string includinga first selection transistor,a first memory cell, anda second memory cell, anda second memory string includinga second selection transistor,a third memory cell, anda fourth memory cell;

    a first bit line connected to the first memory string and the second memory string;

    a first select gate line connected to a gate of the first transistor;

    a second select gate line connected to a gate of the second transistor;

    a first word line connected to a gate of the first memory cell and a gate of the third memory cell;

    a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; and

    a controller configured toperform an erase operation on the first memory cell, the second memory cell, the third memory cell and the fourth memory cell,after the erase operation, perform a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line, andafter the first verify operation, perform a second verify operation on the third memory cell with the first verify voltage applied to the first word line not discharged from the first verify operation and on the fourth memory cell with the second verify voltage applied to the second word line not discharged from the first verify operation.

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