Semiconductor memory device
First Claim
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1. A semiconductor memory device, comprising:
- a memory block includinga first memory string includinga first selection transistor,a first memory cell, anda second memory cell, anda second memory string includinga second selection transistor,a third memory cell, anda fourth memory cell;
a first bit line connected to the first memory string and the second memory string;
a first select gate line connected to a gate of the first transistor;
a second select gate line connected to a gate of the second transistor;
a first word line connected to a gate of the first memory cell and a gate of the third memory cell;
a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; and
a controller configured toperform an erase operation on the first memory cell, the second memory cell, the third memory cell and the fourth memory cell,after the erase operation, perform a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line, andafter the first verify operation, perform a second verify operation on the third memory cell with the first verify voltage applied to the first word line not discharged from the first verify operation and on the fourth memory cell with the second verify voltage applied to the second word line not discharged from the first verify operation.
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Abstract
A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
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Citations
14 Claims
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1. A semiconductor memory device, comprising:
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a memory block including a first memory string including a first selection transistor, a first memory cell, and a second memory cell, and a second memory string including a second selection transistor, a third memory cell, and a fourth memory cell; a first bit line connected to the first memory string and the second memory string; a first select gate line connected to a gate of the first transistor; a second select gate line connected to a gate of the second transistor; a first word line connected to a gate of the first memory cell and a gate of the third memory cell; a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; and a controller configured to perform an erase operation on the first memory cell, the second memory cell, the third memory cell and the fourth memory cell, after the erase operation, perform a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line, and after the first verify operation, perform a second verify operation on the third memory cell with the first verify voltage applied to the first word line not discharged from the first verify operation and on the fourth memory cell with the second verify voltage applied to the second word line not discharged from the first verify operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for operating semiconductor memory device,
the semiconductor memory device including: -
a memory block including a first memory string including a first selection transistor, a first memory cell, and a second memory cell, and a second memory string including a second selection transistor, a third memory cell, and a fourth memory cell; a first bit line connected to the first memory string and the second memory string; a first select gate line connected to a gate of the first transistor; a second select gate line connected to a gate of the second transistor; a first word line connected to a gate of the first memory cell and a gate of the third memory cell; and a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell, the method comprising; performing an erase operation on the first memory cell, the second memory cell, the third memory cell and the fourth memory cell, after the erase operation, performing a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line, and after the first verify operation, performing a second verify operation on the third memory cell with the first verify voltage applied to the first word line not discharged from the first verify operation and on the fourth memory cell with the second verify voltage applied to at the second word line not discharged from the first verify operation. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification
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Current AssigneeKioxia Corporation
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Original AssigneeToshiba Memory Corporation (Kioxia Corporation)
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InventorsTokiwa, Naoya
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Primary Examiner(s)Lappas, Jason
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Application NumberUS15/936,214Publication NumberTime in Patent Office302 DaysField of Search36518529, 36518522, 36518517US Class CurrentCPC Class CodesG11C 16/0466 comprising cells with charg...G11C 16/0483 comprising cells having sev...G11C 16/06 Auxiliary circuits, e.g. fo...G11C 16/08 Address circuits; Decoders;...G11C 16/10 Programming or data input c...G11C 16/16 for erasing blocks, e.g. ar...G11C 16/26 Sensing or reading circuits...G11C 16/3445 Circuits or methods to veri...
