Method and system for a semiconductor device with integrated transient voltage suppression

• US 10,186,509 B2
• Filed: 10/25/2016
• Issued: 01/22/2019
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Kashyap, Avinash Srikrishnan, Sandvik, Peter Micah, McMahon, James Jay, Stevanovic, Ljubisa Dragoljub
• Primary Examiner(s): Henry, Caleb
• Application Number:
  US15/333,868
• Publication Number:
  US 20170294434A1
• Time in Patent Office: 819 Days
• Field of Search: 257 72, 257 77, 257107, 257173, 257174, 257E29211
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7424 having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Claims

1. A thyristor assembly, comprising:

a thyristor formed of a wide-band gap semiconductor material, said thyristor comprising;

a cathode layer formed of N+ semiconductor material;

a buffer layer made of p-type material formed on the cathode layer;

a lower base layer made of a P−

semiconductor material formed on the buffer layer,

an upper base layer formed over a portion of the lower base layer;

an anode layer formed over a portion of the upper base layer;

a gate electrode formed a portion of the anode layer;

an anode contact formed a portion of an anode layer; and

a base electrode formed over a portion of a lower base layer; and

a transient voltage suppression (TVS) device formed of a wide band gap material, said TVS device formed with the thyristor as a single semiconductor device, said TVS device electrically coupled to said thyristor between the gate electrode and the base electrode.

2. The assembly of claim 1, wherein the thyristor and TVS devices are monolithically integrated.

3. The assembly of claim 1, wherein said TVS device comprises silicon carbide (SiC) formed using ion implantation on a surface of said thyristor.

4. The assembly of claim 1, wherein said thyristor comprises silicon carbide (SiC).

5. The assembly of claim 1, wherein said thyristor and said TVS device are formed of a single semiconductor circuit.

6. The assembly of claim 1, wherein said thyristor and said TVS device are formed of separate circuits on a monolithic semiconductor die and coupled electrically using metallic traces between terminals of said thyristor and said TVS.

7. The assembly of claim 1, wherein said TVS device is formed in the upper base layer.

8. The assembly of claim 1, wherein said TVS device is formed in the lower base layer.

9. The assembly of claim 1, further comprising an anode contact formed over a portion of the anode layer.

10. The assembly of claim 1, further comprising a cathode contact formed over a portion of the cathode layer.

11. The assembly of claim 1, wherein said TVS device including a turn-on voltage selected to be less than a predetermined maximum electrical terminal voltage value.