Antifuse cell comprising program transistor and select transistor arranged on opposite sides of semiconductor layer

• US 10,186,515 B2
• Filed: 07/04/2013
• Issued: 01/22/2019
• Est. Priority Date: 07/10/2012
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Hofmann, Franz
• Primary Examiner(s): Nguyen, Duy T
• Application Number:
  US14/413,405
• Publication Number:
  US 20150171094A1
• Time in Patent Office: 2,028 Days
• Field of Search: 257 50, 257530, 257E23147, 438131
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/60 Peripheral circuit regions

Abstract

The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

Claims

1. An anti-fuse cell, comprising:

a first semiconductor layer comprising a single connection region;

a breakdown layer located on the first semiconductor layer, wherein the breakdown layer exhibits a first electrical conductivity prior to an electrical breakdown and a second electrical conductivity after the electrical breakdown;

a first program transistor having a program gate and a body comprising the first semiconductor layer; and

a first select transistor having a select gate and a body comprising the first semiconductor layer;

wherein the program transistor is in series with the first select transistor; and

wherein the program gate and the select gate are arranged on opposite sides of the first semiconductor layer and the breakdown layer.

2. The anti-fuse cell of claim 1, wherein:

the first semiconductor layer comprises a first portion and a second portion separated by the connection region;

the program gate of the first program transistor is located on the first portion of the first semiconductor layer;

a program gate of a second program transistor of a second anti-fuse cell is located on the second portion of the first semiconductor layer; and

the first program transistor is connected in parallel to the second program transistor.

3. The anti-fuse cell of claim 2, wherein the first program transistor is connected in series with a third program transistor of a third anti-fuse cell, wherein a program gate of the third program transistor is located on the first portion of the first semiconductor layer.

4. The anti-fuse cell of claim 3, wherein the program gate and a gate oxide of any of the first program transistor, second program transistor, and third program transistor are shaped such that the electric field of the program gate is concentrated on a point or a line of the gate oxide.

5. The anti-fuse cell of claim 4, wherein the first semiconductor layer comprises an etched region and for any of the first program transistor, the second program transistor, and the third program transistor:

the gate oxide is placed on the first semiconductor layer and at least on a portion of a wall of the etched region; and

the program gate is placed on the gate oxide, so as to realize an angle in correspondence of the etched region.

6. The anti-fuse cell of claim 4, wherein the second anti-fuse cell and the third anti-fuse cell share the first select transistor.

7. The anti-fuse cell of claim 1, wherein the program gate and a gate oxide of the first program transistor are shaped such that the electric field of the gate is concentrated on a point or a line of the gate oxide.

8. The anti-fuse cell of claim 7, wherein the first semiconductor layer comprises an etched region and for the first program transistor:

the gate oxide is placed on the first semiconductor layer and at least on a portion of a wall of the etched region; and

the program gate is placed on the gate oxide, so as to realize an angle in correspondence of the etched region.

9. The anti-fuse cell of claim 1, further comprising a second program transistor, and wherein the first program transistor, the second program transistor, and the first select transistor are arranged in a NOR configuration.

10. The anti-fuse cell of claim 1, further comprising a second program transistor, and wherein the first program transistor, the second program transistor, and the first select transistor are arranged in a NAND configuration.

11. The anti-fuse cell of claim 1, wherein the breakdown layer comprises an insulation layer between the select gate and the first semiconductor layer.

12. The anti-fuse cell of claim 1, wherein the single connection region facilitates current flow from the program gate, through the first semiconductor layer to a contact on the single connection region upon applying a voltage to the program gate.

13. The anti-fuse cell of claim 1, wherein the single connection region is arranged to facilitate current flow from the select gate, through the program transistor after electrical breakdown, and to a contact on the single connection region upon application of a voltage at the select gate.