MOS-varactor design to improve tuning efficiency

• US 10,186,593 B2
• Filed: 04/18/2017
• Issued: 01/22/2019
• Est. Priority Date: 07/01/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Li, Yong
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US15/489,768
• Publication Number:
  US 20180006127A1
• Time in Patent Office: 644 Days
• Field of Search: 257312, 257595
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66174 Capacitors with PN or Schottky junction, e.g. varactors capacitors with PN junction combined with MOS control H01L29/66189
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Claims

1. A gate stack structure for a MOS varactor, comprising:

a substrate including a channel region;

a high-k dielectric layer on the channel region of the substrate;

a P-type work function adjustment layer on the high-k dielectric layer, the P-type work function adjustment layer including a first portion directly contacting the high-k dielectric layer and a second portion laterally directly contacting the high-k dielectric layer and adjacent to the first portion, the first portion having a thickness greater than a thickness of the second portion;

an N-type work function adjustment layer on the P-type work function adjustment layer; and

a metal gate on the N-type work function adjustment layer.

2. The gate stack structure of claim 1, wherein the P-type work function adjustment layer comprises a first TiN layer on a first portion of the high-k dielectric layer and a second TiN layer on the first TiN layer and on a second portion of the high-k dielectric layer;

the first portion of the P-type work function adjustment layer comprises the first TiN layer and a first portion of the second TiN layer on the first TiN layer; and

the second portion of the P-type work function adjustment layer comprises a second portion of the second TiN layer on the second portion of the high-k dielectric layer.

3. The gate stack structure of claim 1, wherein the P-type work function adjustment layer comprises a first TiN layer on a first portion of the high-k dielectric layer, a TaN layer on the first TiN layer, and a second TiN layer on the TaN layer and on a second portion of the high-k dielectric layer;

the first portion of the P-type work function adjustment layer comprises the first TiN layer, the TaN layer, and a first portion of the second TiN layer on the TaN layer; and

the second portion of the P-type work function adjustment layer comprises a second portion of the second TiN layer on the second portion of the high-k dielectric layer.

4. The gate stack structure of claim 1, wherein the P-type work function adjustment layer comprises a first TiN layer on a first portion of the high-k dielectric layer, a second TiN layer on the first TiN layer and on a second portion of the high-k dielectric layer, and a TaN layer on the second TiN layer;

the first portion of the P-type work function adjustment layer comprises the first TiN layer, the first portion of the second TiN layer on the first TiN layer, and a first portion of the TaN on the first portion of the second TiN layer; and

the second portion of the P-type work function adjustment layer comprises a second portion of the second TiN layer on the second portion of the high-k dielectric layer and a second portion of the TaN on the second portion of the second TiN layer.

5. The gate stack structure of claim 1, further comprising a barrier layer disposed between the N-type work function adjustment layer and the metal gate.

6. The gate stack structure of claim 1, wherein the N-type work function adjustment layer comprises TiAl, TiCAl, TiNAl, or TiSiAl.

7. The gate stack structure of claim 1, wherein a ratio of a length of the first portion to a length of the second portion of the P-type work function adjustment layer is in a range between 1/9 and 9.

8. The gate stack structure of claim 1, wherein the metal gate comprises tungsten.

9. A gate stack structure for a MOS varactor, comprising:

a substrate including a channel region;

a high-k dielectric layer on the channel region of the substrate;

a P-type work function adjustment layer on the high-k dielectric layer;

an N-type work function adjustment layer on the P-type work function adjustment layer; and

a metal gate on the N-type work function adjustment layer,

wherein the P-type work function adjustment layer comprises;

a first portion directly contacting the high-k dielectric layer and a second portion directly contacting the high-k dielectric layer and laterally adjacent to the first portion, the first portion being configured to adjust the work function of a PMOS device, and the second portion being configured to adjust the work function of an NMOS device.

10. The gate stack structure of claim 9, wherein the P-type work function adjustment layer comprises a first TiN layer on a first portion of the high-k dielectric layer and a second TiN layer on the first TiN layer and on a second portion of the high-k dielectric layer;

the first portion of the P-type work function adjustment layer comprises the first TiN layer and a first portion of the second TiN layer on the first TiN layer; and

the second portion of the P-type work function adjustment layer comprises a second portion of the second TiN layer on the second portion of the high-k dielectric layer.

11. The gate stack structure of claim 9, wherein the P-type work function adjustment layer comprises a first TiN layer on a first portion of the high-k dielectric layer, a second TiN layer on the first TiN layer and on a second portion of the high-k dielectric layer, and a TaN layer on the second TiN layer;

the first portion of the P-type work function adjustment layer comprises the first TiN layer, the first portion of the second TiN layer on the first TiN layer, and a first portion of the TaN on the first portion of the second TiN layer; and

the second portion of the P-type work function adjustment layer comprises a second portion of the second TiN layer on the second portion of the high-k dielectric layer and a second portion of the TaN on the second portion of the second TiN layer.

12. The gate stack structure of claim 9, wherein a ratio of a length of the first portion to a length of the second portion of the P-type work function adjustment layer is in a range between 1/9 and 9.

13. The gate stack structure of claim 9, wherein the N-type work function adjustment layer comprises TiAl, TiCAl, TiNAl, or TiSiAl.